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precision analog microcontroller, 12-bit analog i/o, arm7tdmi mcu with enhanced irq handler aduc7023 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features analog i/o multichannel, 12-bit, 1 msps adc up to 12 adc channels fully differential and single-ended modes 0 v to v ref analog input range 12-bit voltage output dacs 4 dac outputs available on-chip voltage reference on-chip temperature sensor voltage comparator microcontroller arm7tdmi core, 16-bit/32-bit risc architecture jtag port supports code download and debug clocking options trimmed on-chip oscillator (3%) external watch crystal external clock source up to 44 mhz 41.78 mhz pll with programmable divider memory 62 kb flash/ee memory, 8 kb sram in-circuit download, jtag-based debug software-triggered in-circuit reprogrammability vectored interrupt controller for fiq and irq 8 priority levels for each interrupt type interrupt on edge or level external pin inputs on-chip peripherals 2 fully i 2 c-compatible channels spi (20 mbps in master mode, 10 mbps in slave mode) with 4-byte fifo on input and output stages up to 20 gpio pins all gpios are 5 v tolerant 3 general-purpose timers watchdog timer (wdt) programmable logic array (pla) 16 pla elements 16-bit, 5-channel pwm power specified for 3 v operation active mode: 11 ma at 5 mhz, 28 ma at 41.78 mhz packages and temperature range 32-lead 5 mm 5 mm lfcsp 40-lead lfcsp fully specified for ?40c to +125c operation tools low cost quickstart development system full third-party support applications optical networking industrial control and automation systems smart sensors, precision instrumentation base station systems general description the aduc7023 is a fully integrated, 1 msps, 12-bit data acquisition system, incorporating high performance multichannel adcs, 16-bit/32-bit mcus, and flash/ee memory on a single chip. the adc consists of up to 12 single-ended inputs. an additional four inputs are available but are multiplexed with the four dac output pins. the adc can operate in single-ended or differential input modes. the adc input voltage is 0 v to v ref . a low drift band gap reference, temperature sensor, and voltage comparator complete the adc peripheral set. the dac output range is programmable to one of two voltage ranges. the dac outputs have an enhanced feature of being able to retain their output voltage during a watchdog or software reset sequence. the devices operate from an on-chip oscillator and a pll, generating an internal high frequency clock of 41.78 mhz. this clock is routed through a programmable clock divider from which the mcu core clock operating frequency is generated. the microcontroller core is an arm7tdmi?, 16-bit/32-bit risc machine that offers up to 41 mips peak performance. eight kilobytes of sram and 62 kilobytes of nonvolatile flash/ee memory are provided on chip. the arm7tdmi core views all memory and registers as a single linear array. the aduc7023 contains an advanced interrupt controller. the vectored interrupt controller (vic) allows every interrupt to be assigned a priority level. it also supports nested interrupts to a maximum level of eight per irq and fiq. when irq and fiq interrupt sources are combined, a total of 16 nested interrupt levels are supported. on-chip factory firmware supports in-circuit download via the i 2 c serial interface port, and nonintrusive emulation is supported via the jtag interface. these features are incorporated into a low cost quickstart? development system supporting this microconverter? family. the part contains a 16-bit pwm with five output signals. for communication purposes, the part contains 2 i 2 c channels that can be individually configured for master or slave mode. an spi interface supporting both master and slave modes is also provided. the parts operate from 2.7 v to 3.6 v and are specified over an industrial temperature range of ?40c to +125c. the aduc7023 is available in either a 32-lead or 40-lead lfcsp package.
aduc7023 rev. b | page 2 of 96 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 3 ? functional block diagram .............................................................. 4 ? specifications ..................................................................................... 5 ? timing specifications .................................................................. 8 ? absolute maximum ratings .......................................................... 13 ? esd caution ................................................................................ 13 ? pin configurations and function descriptions ......................... 14 ? typical performance characteristics ........................................... 17 ? terminology .................................................................................... 18 ? adc specifications .................................................................... 18 ? dac specifications..................................................................... 18 ? overview of the arm7tdmi core ............................................. 19 ? thumb mode (t) ........................................................................ 19 ? long multiply (m) ...................................................................... 19 ? embeddedice (i) ....................................................................... 19 ? exceptions ................................................................................... 19 ? arm registers ............................................................................ 19 ? interrupt latency ........................................................................ 20 ? memory organization ................................................................... 21 ? memory access ........................................................................... 21 ? flash/ee memory ....................................................................... 21 ? sram ........................................................................................... 21 ? memory mapped registers ....................................................... 21 ? adc circuit overview .................................................................. 28 ? transfer function ....................................................................... 28 ? typical operation ....................................................................... 29 ? mmr interface ............................................................................ 29 ? converter operation .................................................................. 32 ? driving the analog inputs ........................................................ 33 ? calibration ................................................................................... 33 ? temperature sensor ................................................................... 34 ? band gap reference ................................................................... 35 ? nonvolatile flash/ee memory ..................................................... 36 ? programming .............................................................................. 36 ? security ........................................................................................ 37 ? flash/ee control interface ....................................................... 37 ? execution time from sram and flash/ee ............................ 40 ? reset and remap ........................................................................ 40 ? other analog peripherals .............................................................. 43 ? dac .............................................................................................. 43 ? power supply monitor ............................................................... 45 ? comparator ................................................................................. 45 ? oscillator and pllpower control ........................................ 47 ? digital peripherals .......................................................................... 50 ? general-purpose input/output................................................ 50 ? serial peripheral interface ......................................................... 53 ? i 2 c ..................................................................................................... 58 ? configuring external pins for i 2 c functionality ................... 58 ? serial clock generation ............................................................ 58 ? i 2 c bus addresses ....................................................................... 58 ? i 2 c registers ................................................................................ 59 ? programmable logic array (pla)........................................... 66 ? pulse-width modulator ................................................................. 70 ? pulse-width modulator general overview ........................... 70 ? processor reference peripherals ................................................... 75 ? interrupt system ......................................................................... 75 ? irq ............................................................................................... 75 ? fast interrupt request (fiq) .................................................... 76 ? vectored interrupt controller (vic) ....................................... 77 ? timers .......................................................................................... 82 ? hardware design considerations ................................................ 87 ? power supplies ............................................................................ 87 ? grounding and board layout recommendations ................. 88 ? clock oscillator .......................................................................... 88 ? power-on reset operation ........................................................ 89 ? typical system configuration .................................................. 90 ? development tools......................................................................... 91 ? pc-based tools ........................................................................... 91 ? in-circuit i 2 c downloader ....................................................... 91 ? outline dimensions ....................................................................... 92 ? ordering guide .......................................................................... 93 ?
aduc7023 rev. b | page 3 of 96 revision history 7/10rev. a to rev. b changes to temperature sensor parameter in table 1................. 6 change to table 10 and changes to table 11 ............................... 23 changes to table 12 and table 13 ................................................. 24 changes to table 16 and table 17 ................................................. 25 changes to table 18 ........................................................................ 26 change to table 21 and changes to table 22 ............................... 27 changes to table 24 ........................................................................ 29 changes to adcgn register and adcof register sections .. 32 changes to temperature sensor section ...................................... 34 changes to table 29 ........................................................................ 35 change to remap register and rstclr register sections .... 41 change to rstke1 register and rstke2 register sections ............................................................................................. 42 changes to oscillator and pllpower control section .......... 48 changes to general-purpose input/output section .................. 51 changes to serial peripheral interface section ........................... 53 changes to table 75 ........................................................................ 67 changes to table 83 and pulse-width modulator general overview section ............................................................................ 70 changes to table 84 ........................................................................ 71 change to table 85 .......................................................................... 72 change to fiqstan register section ......................................... 81 change to t2clri register section ............................................. 85 6/10rev. 0 to rev. a changes to temperature sensor parameter in table 1 ................ 6 changes to table 24 ........................................................................ 29 changes to temperature sensor section ..................................... 34 changes to dacbke0 register section and to table 43 ........ 47 changes to ordering guide ........................................................... 93 1/10revision 0: initial version
aduc7023 rev. b | page 4 of 96 functional block diagram 08675-001 aduc7023 40-lead lfcsp dac0 dac1 dac2 dac3 adc0 xclki xclko rst v ref adc12 a dc2/cmp0 a dc3/cmp1 cmp out 12-bit dac 12-bit dac 12-bit dac 12-bit dac vectored interrupt controller 1msps 12-bit adc temp sensor band gap ref mux osc and pll psm por arm7tdmi-based mcu with additional peripherals pla 3 general- purpose timers 2k 32 sram 31k 16 flash/eeprom spi, 2 i 2 c gpio pwm jtag figure 1.
aduc7023 rev. b | page 5 of 96 specifications av dd = iov dd = 2.7 v to 3.6 v, v ref = 2.5 v internal reference, f core = 41.78 mhz, t a = ?40c to +125c, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments adc channel specifications eight acquisition clocks and f adc /2 adc power-up time 5 s dc accuracy 1 , 2 resolution 12 bits integral nonlinearity 0.6 1 .5 lsb 2.5 v internal reference 1.0 lsb 1.0 v external reference differential nonlinearity 3 , 4 0.5 +1/?0.9 lsb 2.5 v internal reference +0.7/?0.6 lsb 1.0 v external reference dc code distribution 1 lsb adc input is a dc voltage endpoint errors 5 offset error 1 2 lsb offset error match 1 lsb gain error 2 lsb gain error match 1 lsb dynamic performance f in = 10 khz sine wave, f sample = 1 msps signal-to-noise ratio (snr) 69 db in cludes distortion and noise components total harmonic distortion (thd) ?78 db peak harmonic or spurious noise ?75 db channel-to-channel crosstalk ?80 db measured on adjacent channels analog input input voltage ranges differential mode v cm v ref /2 6 v single-ended mode 0 to v ref v leakage current 1 6 a input capacitance 20 pf during adc acquisition on-chip voltage reference 0.47 f from v ref to agnd output voltage 2.5 v accuracy 4 mv t a = 25c reference temperature coefficient 15 ppm/c power supply rejection ratio 75 db output impedance 51 t a = 25c internal v ref power-on time 1 ms external reference input input voltage range 0.625 av dd v dac channel specifications dc accuracy 7 r l = 5 k, c l = 100 pf resolution 12 bits relative accuracy 2 lsb differential nonlinearity 1 lsb guaranteed monotonic offset error 15 mv 2.5 v internal reference gain error 8 1 % gain error mismatch 0.1 % % of full scale on dac0 dc accuracy 9 r l = 1 k, c l = 100 pf resolution 12 bits relative accuracy 2.5 lsb differential nonlinearity 1 lsb guaranteed monotonic offset error 15 mv 2.5 v internal reference gain error 10 1 % gain error mismatch 0.1 % % of full scale on dac0 analog outputs output voltage range 1 0 to 2.5 v v ref range: agnd to av dd output voltage range 2 0 to av dd v output impedance 2
aduc7023 rev. b | page 6 of 96 parameter typ max unit test conditions/comments min dac in op amp mode dac output buffer in op amp mode input offset voltage 0.25 mv input offset voltage drift 8 v/c input offset current 0.3 na input bias current 0.4 na gain 80 db 5 k load unity-gain frequency 5 mhz r l = 5 k, c l = 100 pf cmrr 80 db settling time 10 s r l = 5 k, c l = 100 pf output slew rate 1.5 v/s r l = 5 k, c l = 100 pf psrr 75 db dac ac characteristics voltage output settling time 10 s digital-to-analog glitch energy 20 nv-sec 1 lsb change at major carry (where maximum number of bits simultaneously change in the dacxdat register) comparator input offset voltage 10 mv input bias current 1 a input voltage range agnd av dd C 1.2 v input capacitance 7 pf hysteresis 4 , 6 2 15 mv hysteresis can be tu rned on or off via the cmphyst bit in the cmpcon register response time 3 s 100 mv overdrive and configured with cmpres = 11 temperature sensor indicates die temperature voltage output at 25c 1.369 v voltage tc 4.42 mv/c accuracy with no calibration 3 c accuracy with one point calibration using contents of tempref register 1.5 c ja thermal impedance 40-lead lfcsp 26 c/w 32-lead lfcsp 32.5 c/w power supply monitor (psm) iov dd trip point selection 2.79 v one trip point power supply trip point accuracy 2 % of the selected nominal trip point voltage power-on reset 2.41 v watchdog timer (wdt) timeout period 0 512 sec flash/ee memory endurance 11 10,000 cycles data retention 12 20 years t j = 85c digital inputs all digital inputs excluding xclki and xclko logic 1 input current 0.2 1 a v ih = v dd or v ih = 5 v logic 0 input current ?40 ?60 a v il = 0 v; except tdi ?80 ?120 a v il = 0 v; tdi input capacitance 10 pf logic inputs 4 all logic inputs excluding xclki v inl , input low voltage 0.8 v v inh , input high voltage 2.0 v logic outputs all digital outputs excluding xclko v oh , output high voltage 2.4 v i source = 1.6 ma v ol , output low voltage 13 0.4 v i sink = 1.6 ma crystal inputs xclki and xclko logic inputs, xclki only v inl , input low voltage 1.1 v v inh , input high voltage 1.7 v xclki input capacitance 20 pf xclko output capacitance 20 pf
aduc7023 rev. b | page 7 of 96 parameter min typ max unit test conditions/comments internal oscillator 32.768 khz 3 % mcu clock rate from 32 khz internal oscillator 326 khz cd = 7 from 32 khz external crystal 41.78 mhz cd = 0 using an external clock 0.05 44 mhz t a = 85c 0.05 41.78 mhz t a = 125c start-up time core clock = 41.78 mhz at power-on 66 ms from pause/nap mode 24 ns cd = 0 3.07 s cd = 7 from sleep mode 1.58 ms from stop mode 1.7 ms programmable logic array (pla) pin propagation delay 12 ns from input pin to output pin element propagation delay 2.5 ns power requirements 14 , 15 power supply voltage range av dd to agnd and iov dd to dgnd 2.7 3.6 v analog power supply currents av dd current 200 a adc in idle mode digital power supply current iov dd current in normal mode code executing from flash/ee 8.5 10 ma cd = 7 11 15 ma cd = 3 28 35 ma cd = 0 (41.78 mhz clock) iov dd current in pause mode 14 20 ma cd = 0 (41.78 mhz clock) iov dd current in sleep mode 230 650 a t a = 125c additional power supply currents adc 1.4 ma at 1 msps 0.7 ma at 62.5 ksps dac 400 a per dac esd tests 2.5 v reference, t a = 25c hbm passed 3 kv ficdm passed 1.0 kv 1 all adc channel specifications are guaranteed during normal microcontrol ler core operation. 2 apply to all adc input channels. 3 measured using the factory-set default values in the adc offset register (adcof) and gain coefficient register (adcgn). 4 not production tested but supported by design and/or characterization data on production release. 5 measured using the factory-set default values in adcof and adcgn with an external ad845 op amp as an input buffer stage as shown in figure 28. based on external adc system components, the user may need to execute a system calibrat ion to remove external endpoint errors and achieve these speci fications (see the calibration section). 6 the input signal can be centered on any dc common-mode voltage (v cm ) as long as this value is within the adc voltage input range specified. 7 dac linearity is calcul ated using a reduced co de range of 100 to 3995. 8 dac gain error is calculated using a reduced code range of 100 to internal 2.5 v v ref . 9 dac linearity is calcul ated using a reduced co de range of 100 to 3995. 10 dac gain error is calculated using a reduced code range of 100 to internal 2.5 v v ref . 11 endurance is qualified as per jedec standard 22 method a117 and measured at ?40c, +25c, +85c, and +125c. 12 retention lifetime equivalent at junction temperature (t j ) = 85c as per jedec standard 22 method a117. retention lifetime derates with junction temperature. 13 test carried out with a maximum of ei ght i/os set to a low output level. 14 power supply current consumption is measured in normal, pause, and sleep modes under the followin g conditions: no rmal mode wit h 3.6 v supply, pause mode with 3.6 v supply, and sleep mode with 3.6 v supply. 15 iov dd power supply current decreases typically by 2 ma during a flash/ee erase cycle.
aduc7023 rev. b | page 8 of 96 timing specifications table 2. i 2 c timing in fast mode (400 khz) slave master parameter description min max typ unit t l sclk low pulse width 200 1360 ns t h sclk high pulse width 100 1140 ns t shd start condition hold time 300 ns t dsu data setup time 100 740 ns t dhd data hold time 0 400 ns t rsu setup time for repeated start 100 ns t psu stop condition setup time 100 800 ns t buf bus-free time between a stop conditio n and a start condition 1.3 s t r rise time for both sclk and sdata 300 200 ns t f fall time for both sclk and sdata 300 ns table 3. i 2 c timing in standa rd mode (100 khz) slave parameter description min max unit t l sclk low pulse width 4.7 s t h sclk high pulse width 4.0 ns t shd start condition hold time 4.0 s t dsu data setup time 250 ns t dhd data hold time 0 3.45 s t rsu setup time for repeated start 4.7 s t psu stop condition setup time 4.0 s t buf bus-free time between a stop condit ion and a start condition 4.7 s t r rise time for both sclk and sdata 1 s t f fall time for both sclk and sdata 300 ns 08675-002 sdata (i/o) msb lsb ack msb 1 9 8 2?7 1 sclk (i) ps s(r) t r t f t rsu t dsu t dsu t psu t buf t h t f t r t dhd t dhd t shd t sup t l t sup repeated start start condition stop condition figure 2. i 2 c-compatible in terface timing
aduc7023 rev. b | page 9 of 96 table 4. spi master mode timing (phase mode = 1) parameter description min typ max unit t sl sclk low pulse width 1 (spidiv + 1) t uclk ns t sh sclk high pulse width 1 (spidiv + 1) t uclk ns t dav data output valid after sclk edge 25 ns t dsu data input setup time before sclk edge 1 1 t uclk ns t dhd data input hold time after sclk edge 1 2 t uclk ns t df data output fall time 5 12.5 ns t dr data output rise time 5 12.5 ns t sr sclk rise time 5 12.5 ns t sf sclk fall time 5 12.5 ns 1 t uclk = 23.9 ns. it corresponds to the 41.78 mhz internal clock from the pll before the clock divider. 08675-003 mosi msb bit 6 to bit 1 lsb miso msb in bit 6 to bit 1 lsb in sclk (polarity = 0) sclk (polarity = 1) t sf t sr t sl t sh t dav t dsu t dhd t df t dr figure 3. spi master mode timing (phase mode = 1)
aduc7023 rev. b | page 10 of 96 table 5. spi master mode timing (phase mode = 0) parameter description min typ max unit t sl sclk low pulse width 1 (spidiv + 1) t uclk ns t sh sclk high pulse width 1 (spidiv + 1) t uclk ns t dav data output valid after sclk edge 25 ns t dosu data output setup before sclk edge 75 ns t dsu data input setup time before sclk edge 1 1 t uclk ns t dhd data input hold time after sclk edge 1 2 t uclk ns t df data output fall time 5 12.5 ns t dr data output rise time 5 12.5 ns t sr sclk rise time 5 12.5 ns t sf sclk fall time 5 12.5 ns 08675-004 1 t uclk = 23.9 ns. it corresponds to the 41.78 mhz internal clock from the pll before the clock divider. msb bit 6 to bit 1 lsb msb in bit 6 to bit 1 lsb in mosi miso sclk (polarity = 0) sclk (polarity = 1) t sf t sr t sl t dav t sh t df t dr t dosu t dsu t dhd figure 4. spi master mode timing (phase mode = 0)
aduc7023 rev. b | page 11 of 96 table 6. spi slave mode timing (phase mode = 1) parameter description min typ max unit t ss ss to sclk edge 200 ns t sl sclk low pulse width 1 (spidiv + 1) t uclk ns t sh sclk high pulse width 1 (spidiv + 1) t uclk ns t dav data output valid after sclk edge 25 ns t dsu data input setup time before sclk edge 1 1 t uclk ns t dhd data input hold time after sclk edge 1 2 t uclk ns t df data output fall time 5 12.5 ns t dr data output rise time 5 12.5 ns t sr sclk rise time 5 12.5 ns t sf sclk fall time 5 12.5 ns t sfs ss high after sclk edge 0 ns 08675-005 mosi miso sclk (polarity = 0) sclk (polarity = 1) t sf t sfs t sr t sl t dav t sh t df t dr t dsu t dhd ss 1 t uclk = 23.9 ns. it corresponds to the 41.78 mhz internal clock from the pll before the clock divider. msb bit 6 to bit 1 lsb msb in bit 6 to bit 1 lsb in t ss figure 5. spi slave mode timing (phase mode = 1)
aduc7023 rev. b | page 12 of 96 table 7. spi slave mode timing (phase mode = 0) parameter description min typ max unit t ss ss to sclk edge 200 ns t sl sclk low pulse width 1 (spidiv + 1) t uclk ns t sh sclk high pulse width 1 (spidiv + 1) t uclk ns t dav data output valid after sclk edge 25 ns t dsu data input setup time before sclk edge 1 1 t uclk ns t dhd data input hold time after sclk edge 1 2 t uclk ns t df data output fall time 5 12.5 ns t dr data output rise time 5 12.5 ns t sr sclk rise time 5 12.5 ns t sf sclk fall time 5 12.5 ns t docs data output valid after ss edge 25 ns t sfs ss high after sclk edge 0 ns 1 t uclk = 23.9 ns. it corresponds to the 41.78 mhz internal clock from the pll before the clock divider. 08675-006 msb in bit 6 to bit 1 lsb in msb bit 6 to bit 1 lsb mosi miso sclk (polarity = 0) sclk (polarity = 1) t sf t sfs t sr t sl t dav t sh t df t dr t dsu t docs t dhd ss t ss figure 6. spi slave mode timing (phase mode = 0)
aduc7023 rev. b | page 13 of 96 absolute maximum ratings agnd = gnd ref , t a = 25c, unless otherwise noted. table 8. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating can be applied at any one time. esd caution parameter rating av dd to iov dd ?0.3 v to +0.3 v agnd to dgnd ?0.3 v to +0.3 v iov dd to dgnd, av dd to agnd ?0.3 v to +6 v digital input voltage to dgnd ?0.3 v to +5.3 v digital output voltage to dgnd ?0.3 v to iov dd + 0.3 v v ref to agnd ?0.3 v to av dd + 0.3 v analog inputs to agnd ?0.3 v to av dd + 0.3 v analog outputs to agnd ?0.3 v to av dd + 0.3 v operating temperature range, industrial ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 40-lead lfcsp 26c/w 32-lead lfcsp 32.5c/w peak solder reflow temperature snpb assemblies (10 sec to 30 sec) 240c rohs compliant assemblies (20 sec to 40 sec) 260c
aduc7023 rev. b | page 14 of 96 pin configurations and function descriptions notes 1. the lfcsp_vq only has an exposed paddle that must be left unconnected. 08675-048 1 av dd 2 gnd ref 3 dac0 4 dac1 5 dac2 6 dac3 7 p1.4/adc10/plao[3] 8 p2.0/adc12/pwm4/plai[7] 9 10 p0.5/sda0/plai[1]/comp out 23 rtck 24 tms 25 p0.0/ntrst/adc busy plai[8]/bm 26 p0.1/plai[9]/tdo 27 p0.2/plao[8]/tdi 28 p0.3/plao[9]/tck 29 p1.5/adc6/pwm tripinput /plao[4] 30 p2.2/adc7/sync/plao[6] 22 xclko 21 xclki 11 p0.6/miso/scl1/plai[2] 12 p0.7/mos i/sda1/plao[0] 13 p1.0/spiclk/pwm0/plao [1] 15 p1.6/pwm2/scl1/plai[5] 17 d gnd 16 p1.7/pwm3/sda1/plai[6] 18 iov dd 19 lv dd 20 33 p1 .2/adc4/irq2/plai[3]/eclk 34 p1.3/adc5/irq3/plai[4] 35 v ref 36 adc0 37 adc1 38 adc2/cmp0 39 adc3/cmp1 40 agnd 32 p2.4/adc9/plai[10 ] 31 p2.3/adc8/plao[7] aduc7023 top view (not to scale) rst 14 p1.1/ss/irq1/pwm1/plao[2]/ti p0.4/irq0/scl0/plai[0]/conv start figure 7. 08675-007 av dd gnd ref dac0 dac1 dac2 dac3 p0.5/sda0/plai[1]/comp out p0.3/plao[9]/tck p0.2/plao[8]/tdi p0.1/plai[9]/tdo p0.0/ntrst/adc busy /plai[8]/bm tms rtck xclko xclki p0.6/miso/scl1/plai[2] p0.7/mosi/sda1/plao[0] p1.0/spiclk/pw m0/plao[1] dgnd iov dd lv dd agnd adc3/cmp1 adc2/cmp0 adc1 adc0 v ref p1.3/adc5/irq3/plai[4] p1.2/adc4/irq 2/plai[3]/eclk rs t 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 aduc7023 top view (not to scale) notes 1. the lfcsp_vq only has an exposed paddle that must be left unconnected. p1 .1/ss/irq1/pw m1/plao[2]/t1 p0.4/irq0/scl0/plai[0]/conv start figure 8. table 9. pin function descriptions pin no. 40-lfcsp 32-lfcsp mnemonic description 0 0 exposed paddle exposed pad. the lfcsp_vq only has an exposed paddle that must be left unconnected. 36 28 adc0 single-ended or differential analog input 0. 37 29 adc1 single-ended or differential analog input 1. 38 30 adc2/cmp0 single-ended or differential analog input 2/comparator positive input. 39 31 adc3/cmp1 single-ended or differential analog input 3/comparator negative input. 32 n/a p2.4/adc9/plai[10] general-purpose input and output port 2.4/adc single-ended or differential analog input/programmable logic array input element 10. by default, this pin is configured as a digital input with a weak pull-up resistor enabled. 31 n/a p2.3/adc8/plao[7] general-purpose input and output port 2.3/adc single-ended or differential analog input 8/programmable logic array output element 7. by default, this pin is configured as a digital input with a weak pull-up resistor enabled. when used as adc input, pull-up resistor should be disabled manually. 30 n/a p2.2/adc7/sync/plao[6] general-purpose input and output port 2.2/adc single-ended or differential analog input 7/pwm sync /programmable logic array output element 6. by default, this pin is conf igured as a digital input with a weak pull-up resistor enabled. when used as adc input, pull-up resistor should be disabled manually. 8 n/a p2.0/adc12/pwm4/plai[7] general-purpose input and output port 2.0/adc single-ended or differential analog input 12/pwm output 4/programmable logic array input element 7. by default, this pin is configured as a digital input with a weak pull-up resistor enabled. when used as an adc input, it is not possible to disable the internal pull-up resister. this means that this pin has a higher leakage current value than other analog input pins. 2 2 gnd ref ground voltage reference for the adc. for optimal performance, the analog power supply should be separated from dgnd. 3 3 dac0 dac0 voltage output or adc input. 4 4 dac1 dac1 voltage output or adc input.
aduc7023 rev. b | page 15 of 96 pin no. 40-lfcsp 32-lfcsp mnemonic description 5 5 dac2 dac2 voltage output or adc input. 6 6 dac3 dac3 voltage output or adc input. 24 20 tms test mode select, jtag test port input. debug and download access. this pin has an internal pull-up resistor to iov dd . in some cases an external pull-up resistor is also required to ensure the part does not enter an erroneous state. 25 21 p0.0/ntrst/adc busy /plai[8]/bm this is a multifunction pin as follows: general-purpose input and output port 0.0. by default, this pin is configured as gpio. jtag reset input. debug and download access. if this pin is held low, jtag access is not possible because the jtag interface is held in reset and p0.1/p0.2/p0.3 are configured as gpio pins. adc busy signal. programmable logic array input element 8. boot mode entry pin. the aduc7023 enters i 2 c download mode if bm is low at reset with a flash address 0x800014 = 0xfffffffff. the aduc7023 executes code if bm is pulled high at reset or if bm is low at reset with a flash address 0x800014 not equal to 0xfffffffff. 26 22 p0.1/plai[9]/tdo the default value of this pin depends on the level of p0.0/bm. if p0.0/ bm = 0, this pin defaults to a genera l purpose input. if p0.0/bm = 1, this pin defaults to a jtag test data outp ut pin. this is a multifunction pin as follows: general-purpose input and output port 0.1. programmable logic array input element 9. test data out, jtag test port output. debug and download access. when debugging the part via jtag, this pin must not be toggled by user code, and the gp0con/gp0dat register bits affecting this pin can not be changed. 27 23 p0.2/plao[8]/tdi the default value of this pin depends on the level of p0.0/bm. if p0.0/ bm = 0, this pin defaults to a genera l purpose input. if p0.0/bm = 1, this pin defaults to a jtag test data input pin. this is a multifunction pin as follows: general-purpose input and output port 0.2. programmable logic array output element 8. test data in, jtag test port input. debug and download access. when debugging the part via jtag, this pin must not be toggled by user code, and the gp0con/gp0dat register bits affecting this pin must not be changed. 28 24 p0.3/plao[9]/tck the default value of this pin depends on the level of p0.0/bm. if p0.0/bm = 0, this pin defaults to a general pur pose input. if p0.0/bm = 1, this pin defaults to a jtag test data clock pin. this is a multifunction pin as follows: general-purpose input and output port 0.3. programmable logic array output element 9. test clock, jtag test port clock input. debug and download access. when debugging the part via jtag, this pin must not be toggled by user code and the gp0con/gp0dat register bits affecting this pin must not be changed. 17 13 dgnd digital ground. 18 14 iov dd 3.3 v supply for gpio and input of the on-chip voltage regulator. 19 15 lv dd 2.6 v output of the on-chip voltage regulator. this output must be connected to a 0.47 f capacitor to dgnd only. 20 16 rst reset input, active low. 23 19 rtck return jtag clock signal. this is not the standard jtag clock signal. it is an output signal from the jtag controller. if using a 20-lead jtag header, connect to pin 11.
aduc7023 rev. b | page 16 of 96 pin no. 40-lfcsp 32-lfcsp mnemonic description 9 7 p0.4/irq0/scl0/plai[0]/conv general-purpose input and output port 0.4/external interrupt request 0//i 2 c0 clock signal/programmable logic array input element 0/adc external convert start. by default, this pin is configured as a digital input with a weak pull-up resistor enabled. 10 8 p0.5/sda0/plai[1]/comp out general-purpose input and output port 0.5/i 2 c0 data signal/programmable logic array input element 1/voltage comparator output. by default, this pin is configured as a digital input with a weak pull-up resistor enabled. 11 9 p0.6/miso/scl1/plai[2] general-purpose input and output port 0.6/spi miso signal/i 2 c1 clock on 32-lead package/programmable logic array input element 2. by default, this pin is configured as a digital input with a weak pull-up resistor enabled. 12 10 p0.7/mosi/sda1/plao[0] general-purpose input and output port 0.7/spi mosi signal/i 2 c1 data signal on 32-lead package/programmable logic array output element 0. by default, this pin is configured as a digital input with a weak pull-up resistor enabled. 21 17 xclki input to the crystal oscillator inverter and input to the internal clock generator circuits. connect to dgnd if unused. 22 18 xclko output from the crystal oscillator inverter. leave unconnected if unused. 16 n/a p1.7/pwm3/sda1/plai[6] general-purpose input and output port 1.7/pwm output 3/i 2 c data signal/programmable logic array input el ement 6. by default, this pin is configured as a digital input with a weak pull-up resistor enabled. 15 n/a p1.6/pwm2/scl1/plai[5] general-purpose input and output port 1.6/pwm output 2/i 2 c clock signal/programmable logic array input el ement 5. by default, this pin is configured as a digital input with a weak pull-up resistor enabled. 29 n/a p1.5/adc6/pwm tripinput /plao[4] general-purpose input and output port 1.5/adc single-ended or differential analog input 6/pwm tripinput /programmable logic array output element 4. by default, this pin is conf igured as a digital input with a weak pull-up resistor enabled. when used as adc input, the pull-up resistor should be disabled manually. 7 n/a p1.4/adc10/plao[3] general-purpose input and output port 1.4/adc single-ended or differential analog input 10/programmable logic array output element 3. by default, this pin is configured as a digital input with a weak pull-up resistor enabled. when used as adc input, the pull-up resistor should be disabled manually. 34 26 p1.3/adc5/irq3/plai[4] general-purpose input and output port 1.3/adc single-ended or differential analog input 5/extern al interrupt request 3/programmable logic array input element 4. by default, this pin is configured as a digital input with a weak pull-up resistor enabled. when used as adc input, the pull-up resistor should be disabled manually. 33 25 p1.2/adc4/irq2/plai[3]/eclk/ general-purpose input and output port 1.2/adc single-ended or differential analog input 4/extern al interrupt request 2/programmable logic array input element 3/input-output for external clock. by default, this pin is configured as a digital input with a weak pull-up resistor enabled. when used as adc input, the pull-up resistor should be disabled manually. 14 12 p1.1/ ss /irq1/pwm1/plao[2]/t1 general-purpose input and output port 1.1/spi interface slave select (active low)/external interrupt request 1/pwm output 1/programmable logic array output element 2/timer 1 inp ut clock. by default, this pin is configured as a digital input with a weak pull-up resistor enabled. 13 11 p1.0/spiclk/pwm0/plao[1] general-purpose input and output port 1.0/spi interface clock signal/ pwm output 0/programmable logic arra y output element 1. by default, this pin is configured as a digital input with a weak pull-up resistor enabled. 35 27 v ref 2.5 v internal voltage reference. must be connected to a 0.47 f capacitor when using the internal reference. 40 32 agnd analog ground. ground reference point for the analog circuitry. 1 1 av dd 3.3 v analog power.
aduc7023 rev. b | page 17 of 96 typical performance characteristics 0.5 0.6 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 0 500 1000 1500 2000 2500 3000 3500 4095 adc codes dnl (lsb) 08675-049 sampling rate = 950ksps worst case positive = 0.63, code = 2364 worst case negative = ?0.46, code = 2363 figure 9. typical dnl, f adc = 950 ksps, internal reference used 0.6 0.4 0.2 0 ?0.2 ?0.6 ?0.4 ?0.8 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4095 adc codes inl (lsb) 08675-050 sampling rate = 950ksps worst case positive = 0.57, code = 4063 worst case negative = ?0.90, code = 3356 figure 10. typical inl, f adc = 950 ksps, internal reference used 0.6 0.5 0.4 0.3 0.2 0.1 ?0.1 0 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 0 500 1000 1500 2000 2500 3000 3500 4095 adc codes dnl (lsb) 08675-051 sampling rate = 950ksps worst case positive = 0.64, code = 3583 worst case negative = ?0.61, code = 1830 figure 11. typical dnl, f adc = 950 ksps, external 1.0 v reference used 1.2 1.0 0.8 0.6 0.4 0.2 ?0.2 0 ?0.4 ?0.6 ?0.8 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4095 adc codes inl (lsb) 08675-052 sampling rate = 950ksps worst case positive = 1.09, code = 4032 worst case negative = ?0.98, code = 3422 figure 12. typical inl, f adc = 950 ksps, external 1.0 v reference used 20 0 ?20 ?40 ?60 ?80 ?100 ?200 ?400 0 20,000 40,000 60,000 80,000 104,400 frequency (hz) sinad, thd and phsn of adc (db) 08675-053 figure 13. sinad, thd, and phsn of adc , internal 2.5 v reference used
aduc7023 rev. b | page 18 of 96 terminology adc specifications integral nonlinearity (inl) the maximum deviation of any code from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point lsb below the first code transition, and full scale, a point lsb above the last code transition. differential nonlinearity (dnl) the difference between the measured and the ideal 1 lsb change between any two adacent codes in the adc. offset error the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, that is, + lsb. gain error the deviation of the last code transition from the ideal ain voltage (full scale 1.5 lsb) after the offset error has been adusted out. signal to (noise + distortion) ratio the measured ratio of signal to (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent upon the number of quantization levels in the digitization process the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by signal to noise distortion . n . tus for a it converter tis is . total harmonic distortion the ratio of the rms sum of the harmonics to the fundamental. dac specifications relative accuracy otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adusting for zero error and full-scale error. voltage output settling time the amount of time it takes the output to settle to within a 1 lsb level for a full-scale input change.
aduc7023 rev. b | page 19 of 96 overview of the arm7tdmi core the arm7? core is a 32-bit reduced instruction set computer (risc). it uses a single 32-bit bus for instruction and data. the length of the data can be 8 bits, 16 bits, or 32 bits. the length of the instruction word is 32 bits. the arm7tdmi is an arm7 core with four additional features: t support for the thumb (16-bit) instruction set, d support for debug, m support for long multiplications, and i includes the embeddedice module to support embedded system debugging thumb mode (t) an arm instruction is 32 bits long. the arm7tdmi processor supports a second instruction set that has been compressed into 16 bits, called the thumb? instruction set. faster execution from 16-bit memory and greater code density can usually be achieved by using the thumb instruction set instead of the arm instruction set, which makes the arm7tdmi core particularly suitable for embedded applications. however, the thumb mode has two limitations. thumb code typically requires more instructions for the same job. as a result, arm code is usually best for maximizing the performance of time critical code. also, the thumb instruction set does not include some of the instructions needed for exception handling, which automatically switches the core to arm code for exception handling. see the arm7tdmi user guide for details on the core architecture, the programming model, and both the arm and arm thumb instruction sets. long multiply (m) the arm7tdmi instruction set includes four extra instruc- tions that perform 32-bit by 32-bit multiplication with a 64-bit result, and 32-bit by 32-bit multiplication-accumulation (mac) with a 64-bit result. these results are achieved in fewer cycles than required on a standard arm7 core. embeddedice (i) embeddedice provides integrated on-chip support for the core. the embeddedice module contains the breakpoint and watch- point registers that allow code to be halted for debugging purposes. these registers are controlled through the jtag test port. when a breakpoint or watchpoint is encountered, the processor halts and enters debug state. once in a debug state, the processor registers can be inspected as well as the flash/ee, sram, and memory mapped registers. exceptions a rm supports five types of exceptions and a privileged processing mode for each type. the five types of exceptions are: ? normal interrupt or irq. this is provided to service general-purpose interrupt handling of internal and external events. ? fast interrupt or fiq. this is provided to service data transfers or communication channels with low latency. fiq has priority over irq. ? memory abort. ? attempted execution of an undefined instruction. ? software interrupt instruction (swi). this can be used to make a call to an operating system. typically, the programmer defines interrupt as irq, but for higher priority interrupt, that is, faster response time, the programmer can define interrupt as fiq. arm registers arm7tdmi has a total of 37 registers: 31 general-purpose registers and six status registers. each operating mode has dedicated banked registers. when writing user-level programs, 15 general-purpose 32-bit registers (r0 to r14), the program counter (r15), and the current program status register (cpsr) are usable. the remaining registers are only used for system-level programming and exception handling. when an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. all excep- tion modes have replacement banked registers for the stack pointer (r13) and the link register (r14) as represented in figure 14 . the fast interrupt mode has more registers (r8 to r12) for fast interrupt processing. this means the interrupt processing can begin without the need to save or restore these registers, and thus save critical time in the interrupt handling process. 08675-008 usable in user mode system modes only spsr_und spsr_irq spsr_abt spsr_svc r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq r13_und r14_und r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 (pc) r13_irq r14_irq r13_abt r14_abt r13_svc r14_svc spsr_fiq cpsr user mode fiq mode svc mode abort mode irq mode undefined mode figure 14. regist er organization
aduc7023 rev. b | page 20 of 96 more information relative to the model of the programmer and the arm7tdmi core architecture can be found in arm7tdmi technical and arm architecture manuals available directly from arm ltd. interrupt latency the worst-case latency for a fast interrupt request (fiq) consists of the following: the longest time the request can take to pass through the synchronizer, the time for the longest instruction to complete (the longest instruction is an ldm) that loads all the registers including the pc, and the time for the data abort and fiq entry. at the end of this time, the arm7tdmi executes the instruc- tion at 0x1c (fiq interrupt vector address). the maximum total time is 50 processor cycles, which is just under 1.2 s in a system using a continuous 41.78 mhz processor clock. the maximum interrupt request (irq) latency calculation is similar but must allow for the fact that fiq has higher priority and could delay entry into the irq handling routine for an arbitrary length of time. this time can be reduced to 42 cycles if the ldm command is not used. some compilers have an option to compile without using this command. another option is to run the part in thumb mode where the time is reduced to 22 cycles. the minimum latency for fiq or irq interrupts is a total of five cycles, which consist of the shortest time the request can take through the synchronizer, plus the time to enter the exception mode. the arm7tdmi always runs in arm (32-bit) mode when in privileged modes, for example, when executing interrupt service routines.
aduc7023 rev. b | page 21 of 96 memory organization the aduc7023 incorporates two separate blocks of memory: 8 kb of sram and 64 kb of on-chip flash/ee memory; 62 kb of on-chip flash/ee memory is available to the user, and the remaining 2 kb are reserved for the factory configured boot page. these two blocks are mapped as shown in figure 15 . reserved mmrs 0xffffffff 0x0008ffff 0x00011fff 0x0000ffff 0x00000000 0x00010000 0x00080000 0xffff0000 reserved flash/ee (flash/ee or sram) remappable memory space sram 08675-009 figure 15. physical memory map by default, after a reset, the flash/ee memory is mirrored at address 0x00000000. it is possible to remap the sram at address 0x00000000 by clearing bit 0 of the remap mmr. this remap function is described in more detail in the flash/ee memory section. memory access the arm7 core sees memory as a linear array of the 2 32 byte location where the different blocks of memory are mapped as outlined in figure 15 . the aduc7023 memory organizations are configured in little endian format, which means that the least significant byte is located in the lowest byte address, and the most significant byte is in the highest byte address. 0 8675-010 bit 31 byte 2 a 6 2 . . . byte 3 b 7 3 . . . byte 1 9 5 1 . . . byte 0 8 4 0 . . . bit 0 32 bits 0xffffffff 0x00000004 0x00000000 figure 16. little endian format flash/ee memor the total 64 kb of flash/ee memory is organized as 32k 16 bits; 31k 16 bits is user space and 1 k 16 bits is reserved for the on-chip kernel. the page size of th is flash/ee memory is 512 bytes. 62 kilobytes of flash/ee memory are available to the user as code and nonvolatile data memory. there is no distinction between data and program because arm code shares the same space. the real width of the flash/ee memory is 16 bits, which means that in arm mode (32-bit instruction), two accesses to the flash/ee are necessary for each instruction fetch. it is, therefore, recommended to use thumb mode when executing from flash/ee memory for optimum access speed. the maximum access speed for the flash/ee memory is 41.78 mhz in thumb mode and 20.89 mhz in full arm mode. more details about flash/ee access time are outlined later in the execution time from sram and flash/ee section. sram eight kilobytes of sram are available to the user, organized as 2k 32 bits, that is, two words. arm code can run directly from sram at 41.78 mhz, given that the sram array is configured as a 32-bit wide memory array. more details about sram access time are outlined later in the execution time from sram and flash/ee section. memory mapped registers the memory mapped register (mmr) space is mapped into the upper two pages of the memory array and accessed by indirect addressing through the arm7 banked registers. the mmr space provides an interface between the cpu and all on-chip peripherals. all registers, except the core registers, reside in the mmr area. all shaded locations shown in figure 17 are unoccupied or reserved locations and should not be accessed by user software. tabl e 10 to table 23 show the full mmr memory map. the access time for reading from or writing to an mmr depends on the advanced microcontroller bus architecture (amba) bus used to access the peripheral. the processor has two amba buses: advanced high performance bus (ahb) used for system modules and advanced peripheral bus (apb) used for lower performance peripheral. access to the ahb is one cycle, and access to the apb is two cycles. all peripherals on the aduc7023 are on the apb except the flash/ee memory and the gpios.
aduc7023 rev. b | page 22 of 96 flash control interface gpio pla spi i 2 c1 i 2 c0 dac adc band gap reference power supply monitor pll and oscillator control watchdog timer general-purpose timer timer0 remap and system control interrupt controller 0xfffffff f 0xfffff820 0xfffff800 0xfffff46c 0xfffff400 0xffff0fbf 0xffff0f80 0xffff0b54 0xffff0b00 0xffff0a14 0xffff0a00 0xffff0948 0xffff0900 0xffff0848 0xffff0800 0xffff0620 0xffff0600 0xffff0538 0xffff0500 0xffff0490 0xffff048c 0xffff0448 0xffff0440 0xffff0420 0xffff0404 0xffff0370 0xffff0360 0xffff0334 0xffff0320 0xffff0310 0xffff0300 0xffff0238 0xffff0220 0xffff0140 0xffff0000 08675-011 pwm figure 17. memory mapped registers
aduc7023 rev. b | page 23 of 96 table 10. irq address base = 0xffff0000 address name byte access type default value description 0x0000 irqsta 4 r 0x00000000 active irq source. 0x0004 irqsig 4 r current state of all irq sources (enabled and disabled). 0x0008 irqen 4 r/w 0x00000000 enabled irq sources. 0x000c irqclr 4 w mmr to disable irq sources. 0x0010 swicfg 4 w software interrupt configuration mmr. 0x0014 irqbase 4 r/w 0x00000000 base address of all vectors. points to start of a 64-byte memory block which can contain up to 32 pointers to separate subroutine handlers. 0x001c irqvec 4 r 0x00000000 this register contains the subroutine address for the currently active irq source. 0x0020 irqp0 4 r/w 0x00000000 this register contains the interrupt pr iority setting for interrupt source 1 to interrupt source 7. an interrupt can have a priority setting of 0 to 7. 0x0024 irqp1 4 r/w 0x00000000 this register contains the interrupt pr iority setting for interrupt source 8 to interrupt source 15. 0x0028 irqp2 4 r/w 0x00000000 this register contains the interrupt priority setting for interrupt source 16 to interrupt source 21. 0x002c reserved 4 r/w 0x00000000 reserved. 0x0030 irqconn 4 r/w 0x00000000 used to enable irq and fiq interrupt nesting. 0x0034 irqcone 4 r/w 0x00000000 this register configures the external interrupt sources as rising edge, falling edge, or level triggered. 0x0038 irqclre 4 r/w 0x00000000 used to clear an edge level triggered interrupt source. 0x003c irqstan 4 r/w 0x00000000 this register indicates the priority level of an interrupt that has just caused an interrupt exception. 0x0100 fiqsta 4 r 0x00000000 active fiq source. 0x0104 fiqsig 4 r current state of all fiq sources (enabled and disabled). 0x0108 fiqen 4 r/w 0x00000000 enabled fiq sources. 0x010c fiqclr 4 w mmr to disable fiq sources. 0x011c fiqvec 4 r 0x00000000 fiq interrupt vector. 0x013c fiqstan 4 rw 0x00000000 this register indicates the priority level of an fiq that has just caused an fiq exception. table 11. system control address base = 0xffff0200 address name byte access type default value 1 description 0x0220 remap 2 1 r/w 0x00 remap control register. 0x0230 rststa 1 r/w 0x01 rststa status mmr. 0x0234 rstclr 1 w 0x00 rstclr mmr for clearing rststa register. 0x0248 rstkey1 1 w 0xxx 0x76 should be written to this register before writing to rstcfg. 0x024c rstcfg 1 r/w 0x00 this register allows the dac and gpio outputs to retain state after a watchdog or software reset. 0x0250 rstkey2 1 w 0xxx 0xb1 should be written to this register after writing to rstcfg. 1 n/a means not applicable. 2 updated by kernel.
aduc7023 rev. b | page 24 of 96 table 12. timer address base = 0xffff0300 address name byte access type default value 1 description 0x0300 t0ld 2 r/w 0x0000 timer0 load register. 0x0304 t0val 2 r 0xffff timer0 value register. 0x0308 t0con 2 r/w 0x0000 timer0 control mmr. 0x030c t0clri 1 w 0xxx timer0 interrupt clear register. 0x0320 t1ld 4 r/w 0x00000000 timer1 load register. 0x0324 t1val 4 r 0xffffffff timer1 value register 0x0328 t1con 4 r/w 0x00000000 timer1 control mmr. 0x032c t1clri 1 w 0xxx timer1 interrupt clear register. 0x0330 t1cap 4 r 0x00000000 timer1 capture register. 0x0360 t2ld 2 r/w 0x0000 timer2 load register. 0x0364 t2val 2 r 0xffff timer2 value register. 0x0368 t2con 2 r/w 0x0000 timer2 control mmr. 0x036c t2clri 1 w 0xxx timer2 interrupt clear register. 1 n/a means not applicable. table 13. pll/psm base address = 0xffff0400 address name byte access type default value 1 description 0x0404 powkey1 2 w 0xxxxx powcon0 prewrite key. 0x0408 powcon0 1 r/w 0x00 power control and core speed control register. 0x040c powkey2 2 w 0xxxxx powcon0 postwrite key. 0x0410 pllkey1 2 w 0xxxxx pllcon prewrite key. 0x0414 pllcon 1 r/w 0x21 pll clock source selection mmr. 0x0418 pllkey2 2 w 0xxxxx pllcon postwrite key. 0x0434 powkey3 2 w 0xxxxx powcon1 prewrite key. 0x0438 powcon1 2 r/w 0x0004 power control and core speed control register. 0x043c powkey4 2 w 0xxxxx powcon1 postwrite key. 0x0440 psmcon 2 r/w 0x0008 power supply monitor control register. 0x0444 cmpcon 2 r/w 0x0000 comparator control register. 1 n/a means not applicable. table 14. reference base address = 0xffff0480 address: 0x048c name: refcon byte: 1 access type: read/write default value: 0x00 description: reference control register. table 15. adc address base = 0xffff0500 address name byte access type default value description 0x0500 adccon 2 r/w 0x0600 adc control mmr. 0x0504 adccp 1 r/w 0x00 adc positive channel selection register. 0x0508 adccn 1 r/w 0x01 adc negative channel selection register. 0x050c adcsta 1 r 0x00 adc status mmr. 0x0510 adcdat 4 r 0x00000000 adc data output mmr. 0x0514 adcrst 1 r/w 0x00 adc reset mmr.
aduc7023 rev. b | page 25 of 96 address name byte access type default value description 0x0530 adcgn 2 r/w factory configured adc gain calibration mmr. 0x0534 adcof 2 r/w factory configured adc offset calibration mmr. 0x0544 tscon 1 r/w 0x00 temperature sensor chopping enable register. 0x0548 tempref 2 r/w factory configured temperature sensor reference value. table 16. dac address base = 0xffff0600 address name byte access type default value description 0x0600 dac0con 1 r/w 0x00 dac0 control mmr. 0x0604 dac0dat 4 r/w 0x00000000 dac0 data mmr. 0x0608 dac1con 1 r/w 0x00 dac1 control mmr. 0x060c dac1dat 4 r/w 0x00000000 dac1 data mmr. 0x0610 dac2con 1 r/w 0x00 dac2 control mmr. 0x0614 dac2dat 4 r/w 0x00000000 dac2 data mmr. 0x0618 dac3con 1 r/w 0x00 dac3 control mmr. 0x061c dac3dat 4 r/w 0x00000000 dac3 data mmr. 0x0654 dacbcfg 1 r/w 0x00 dac configuration mmr 0x0650 dacbkey0 2 w 0x0000 dac key0 mmr 0x0658 dacbkey1 2 w 0x0000 dac key1 mmr table 17. i 2 c0 base address = 0xffff0800 address name byte access type default value description 0x0800 i2c0mcon 2 r/w 0x0000 i 2 c0 master control register. 0x0804 i2c0msta 2 r 0x0000 i 2 c0 master status register. 0x0808 i2c0mrx 1 r 0x00 i 2 c0 master receive register. 0x080c i2c0mtx 1 w 0x00 i 2 c0 master transmit register. 0x0810 i2c0mcnt0 2 r/w 0x0000 i 2 c0 master read count register. write the number of required bytes into this register prior to reading from a slave device. 0x0814 i2c0mcnt1 1 r 0x00 i 2 c0 master current read count register. this register contains the number of bytes already received during a read from slave sequence. 0x0818 i2c0adr0 1 r/w 0x00 i 2 c0 address byte register. write the required slave address in here prior to communications. 0x081c i2c0adr1 1 r/w 0x00 i 2 c0 address byte register. write the required slave address in here prior to communications. used in 10-bit mode only. 0x0824 i2c0div 2 r/w 0x1f1f i 2 c0 clock control register. used to configure the sclk frequency. 0x0828 i2c0scon 2 r/w 0x0000 i 2 c0 slave control register. 0x082c i2c0ssta 2 r/w 0x0000 i 2 c0 slave status register. 0x0830 i2c0srx 1 r 0x00 i 2 c0 slave receive register. 0x0834 i2c0stx 1 w 0x00 i 2 c0 slave transmit register. 0x0838 i2c0alt 1 r/w 0x00 i 2 c0 hardware general call recognition register. 0x083c i2c0id0 1 r/w 0x00 i 2 c0 slave id0 register. slave bus id register. 0x0840 i2c0id1 1 r/w 0x00 i 2 c0 slave id1 register. slave bus id register. 0x0844 i2c0id2 1 r/w 0x00 i 2 c0 slave id2 register. slave bus id register. 0x0848 i2c0id3 1 r/w 0x00 i 2 c0 slave id3 register. slave bus id register. 0x084c i2c0fsta 2 r/w 0x0000 i 2 c0 fifo status register. used in both master and slave modes. table 18. i 2 c1 base address = 0xffff0900 address name byte access type default value description 0x0900 i2c1mcon 2 r/w 0x0000 i 2 c1 master control register. 0x0904 i2c1msta 2 r 0x0000 i 2 c1 master status register. 0x0908 i2c1mrx 1 r 0x00 i 2 c1 master receive register. 0x090c i2c1mtx 1 w 0x00 i 2 c1 master transmit register. 0x0910 i2c1mcnt0 2 r/w 0x0000 i 2 c1 master read count register. write the number of required bytes into this register prior to reading from a slave device.
aduc7023 rev. b | page 26 of 96 address name byte access type default value description 0x0914 i2c1mcnt1 1 r 0x00 i 2 c1 master current read count register. this register contains the number of bytes already received during a read from slave sequence. 0x0918 i2c1adr0 1 r/w 0x00 i 2 c1 address byte register. write the required slave address in here prior to communications. 0x091c i2c1adr1 1 r/w 0x00 i 2 c1 address byte register. write the required slave address in here prior to communications. used in 10-bit mode only. 0x0924 i2c1div 2 r/w 0x1f1f i 2 c1 clock control register. used to configure the sclk frequency. 0x0928 i2c1scon 2 r/w 0x0000 i 2 c1 slave control register. 0x092c i2c1ssta 2 r/w 0x0000 i 2 c1 slave status register. 0x0930 i2c1srx 1 r 0x00 i 2 c1 slave receive register. 0x0934 i2c1stx 1 w 0x00 i 2 c1 slave transmit register. 0x0938 i2c1alt 1 r/w 0x00 i 2 c1 hardware general call recognition register. 0x093c i2c1id0 1 r/w 0x00 i 2 c1 slave id0 register. slave bus id register. 0x0940 i2c1id1 1 r/w 0x00 i 2 c1 slave id1 register. slave bus id register. 0x0944 i2c1id2 1 r/w 0x00 i 2 c1 slave id2 register. slave bus id register. 0x0948 i2c1id3 1 r/w 0x00 i 2 c1 slave id3 register. slave bus id register. 0x094c i2c1fsta 2 r/w 0x0000 i 2 c1 fifo status register. used in both master and slave modes. table 19. spi base address = 0xffff0a00 address name byte access type default value description 0x0a00 spista 2 r 0x0000 spi status mmr. 0x0a04 spirx 1 r 0x00 spi receive mmr. 0x0a08 spitx 1 w 0xxx spi transmit mmr. 0x0a0c spidiv 1 r/w 0x00 spi baud rate select mmr. 0x0a10 spicon 2 r/w 0x0000 spi control mmr. table 20. pla base address = 0xffff0b00 address name byte access type default value description 0x0b00 plaelm0 2 r/w 0x0000 pla element 0 control register. 0x0b04 plaelm1 2 r/w 0x0000 pla element 1 control register. 0x0b08 plaelm2 2 r/w 0x0000 pla element 2 control register. 0x0b0c plaelm3 2 r/w 0x0000 pla element 3 control register. 0x0b10 plaelm4 2 r/w 0x0000 pla element 4 control register. 0x0b14 plaelm5 2 r/w 0x0000 pla element 5 control register. 0x0b18 plaelm6 2 r/w 0x0000 pla element 6 control register. 0x0b1c plaelm7 2 r/w 0x0000 pla element 7 control register. 0x0b20 plaelm8 2 r/w 0x0000 pla element 8 control register. 0x0b24 plaelm9 2 r/w 0x0000 pla element 9 control register. 0x0b28 plaelm10 2 r/w 0x0000 pla element 10 control register. 0x0b2c plaelm11 2 r/w 0x0000 pla element 11 control register. 0x0b30 plaelm12 2 r/w 0x0000 pla element 12 control register. 0x0b34 plaelm13 2 r/w 0x0000 pla element 13 control register. 0x0b38 plaelm14 2 r/w 0x0000 pla element 14 control register. 0x0b3c plaelm15 2 r/w 0x0000 pla element 15 control register. 0x0b40 placlk 1 r/w 0x00 pla clock select register. 0x0b44 plairq 4 r/w 0x00000000 pla interrupt control register. 0x0b48 plaadc 4 r/w 0x00000000 pla adc trigger control register. 0x0b4c pladin 4 r/w 0x00000000 pla data in register. 0x0b50 pladout 4 r 0x00000000 pla data out register. 0x0b54 plalck 1 w 0x00 pla lock register.
aduc7023 rev. b | page 27 of 96 table 21. pwm base address = 0xffff0f80 address name byte access type default value description 0x0f80 pwmcon1 2 r/w 0x0012 pwm control register 1. see the pulse-width modulator section for full details. 0x0f84 pwm0com0 2 r/w 0x0000 compare regist er 0 for pwm output 0 and pwm output 1. 0x0f88 pwm0com1 2 r/w 0x0000 compare regist er 1 for pwm output 0 and pwm output 1. 0x0f8c pwm0com2 2 r/w 0x0000 compare regist er 2 for pwm output 0 and pwm output 1. 0x0f90 pwm0len 2 r/w 0x0000 frequency cont rol for pwm output 0 and pwm output 1. 0x0f94 pwm1com0 2 r/w 0x0000 compare regist er 0 for pwm output 2 and pwm output 3. 0x0f98 pwm1com1 2 r/w 0x0000 compare regist er 1 for pwm output 2 and pwm output 3. 0x0f9c pwm1com2 2 r/w 0x0000 compare regist er 2 for pwm output 2 and pwm output 3. 0x0fa0 pwm1len 2 r/w 0x0000 frequency cont rol for pwm output 2 and pwm output 3. 0x0fa4 pwm2com0 2 r/w 0x0000 compare regist er 0 for pwm output 4 and pwm output 5. 0x0fa8 pwm2com1 2 r/w 0x0000 compare regist er 1 for pwm output 4 and pwm output 5. 0x0fb8 pwmclri 2 w 0x0000 pwm interrupt clear register. writing any value to this register clears a pwm interrupt source. table 22. gpio base address = 0xfffff400 address name byte access type default value description 0xf400 gp0con 4 r/w 0x00001111 gpio port0 control mmr. 0xf404 gp1con 4 r/w 0x00000000 gpio port1 control mmr. 0xf408 gp2con 4 r/w 0x00000000 gpio port2 control mmr. 0xf420 gp0dat 4 r/w 0x000000xx gpio port0 data control mmr. 0xf424 gp0set 4 w 0x000000xx gpio port0 data set mmr. 0xf428 gp0clr 4 w 0x000000xx gpio port0 data clear mmr. 0xf42c gp0par 4 r/w 0x22220000 gpio port0 pull-up disable mmr. 0xf430 gp1dat 4 r/w 0x000000xx gpio port1 data control mmr. 0xf434 gp1set 4 w 0x000000xx gpio port1 data set mmr. 0xf438 gp1clr 4 w 0x000000xx gpio port1 data clear mmr. 0xf43c gp1par 4 r/w 0x22000022 gpio port1 pull-up disable mmr. 0xf440 gp2dat 4 r/w 0x000000xx gpio port2 data control mmr. 0xf444 gp2set 4 w 0x000000xx gpio port2 data set mmr. 0xf448 gp2clr 4 w 0x000000xx gpio port2 data clear mmr. 0xf44c gp2par 4 r/w 0x00000000 gpio port2 pull-up disable mmr. table 23. flash/ee base address = 0xfffff800 address name byte access type default value description 0xf800 feesta 1 r 0x20 flash/ee status mmr. 0xf804 feemod 2 r/w 0x0000 flash/ee control mmr. 0xf808 feecon 1 r/w 0x07 flash/ee control mmr. 0xf80c feedat 2 r/w 0xxxxx flash/ee data mmr. 0xf810 feeadr 2 r/w 0x0000 flash/ee address mmr. 0xf818 feesign 3 r 0xffffff flash/ee lfsr mmr. 0xf81c feepro 4 r/w 0x00000000 flash/ee protection mmr. 0xf820 feehide 4 r/w 0xffffffff flash/ee protection mmr.
aduc7023 rev. b | page 28 of 96 adc circuit overview the analog-to-digital converter (adc) incorporates a fast, multichannel, 12-bit adc. it can operate from 2.7 v to 3.6 v supplies and is capable of providing a throughput of up to 1 msps when the clock source is 41.78 mhz. this block provides the user with a multichannel multiplexer, a differential track-and-hold, an on-chip reference, and an adc. the adc consists of a 12-bit successive approximation converter based around two capacitor dacs. depending on the input signal configuration, the adc can operate in one of three different modes: fully differential mode (for small and balanced signals), single-ended mode (for any single-ended signals), or pseudo differential mode (for any single-ended signals), taking advantage of the common-mode rejection offered by the pseudo differential input. the converter accepts an analog input range of 0 v to v ref when operating in single-ended or pseudo differential mode. in fully differential mode, the input signal must be balanced around a common-mode voltage (v cm ) in the 0 v to av dd range with a maximum amplitude of 2 v ref (see figure 18 ). 08675-012 av dd v cm v cm v cm 0 2v ref 2v ref 2v ref figure 18. examples of balanced signals in fully differential mode a high precision, low drift, factory calibrated, 2.5 v reference is provided on chip. an external reference can also be connected as described later in the band gap reference section. single or continuous conversion modes can be initiated in the software. an external conv start pin, an output generated from the on-chip pla, or a timer0 or timer1 overflow can also be used to generate a repetitive trigger for adc conversions. a voltage output from an on-chip band gap reference propor- tional to absolute temperature can also be routed through the front-end adc multiplexer. this temperature channel can be selected as an adc input. this facilitates an internal temperature sensor channel that measures die temperature. transfer function pseudo differential and single-ended modes in pseudo differential or single-ended mode, the input range is 0 v to v ref . the output coding is straight binary in pseudo differential and single-ended modes with 1 lsb = fs /4096, or 2.5 v/4096 = 0.61 mv, or 610 v when v ref = 2.5 v the ideal code transitions occur midway between successive integer lsb values (that is, 1/2 lsb, 3/2 lsb, 5/2 lsb, , fs ? 3/2 lsb). the ideal input/output transfer characteristic is shown in figure 19 . 08675-013 output code voltage input 1111 1111 1111 1111 1111 1110 1111 1111 1101 1111 1111 1100 0000 0000 0011 1lsb0v +fs ? 1lsb 0000 0000 0010 0000 0000 0001 0000 0000 0000 1lsb = fs 4096 figure 19. adc transfer function in pseudo differential or single-ended mode fully differential mode the amplitude of the differential signal is the difference between the signals applied to the v in+ and v inC pins (that is, v in+ ? v in? ). the maximum amplitude of the differential signal is, therefore, ?v ref to +v ref p-p (that is, 2 v ref ). this is regardless of the common mode (cm). the common mode is the average of the two signals, for example, (v in+ + v inC )/2, and is, therefore, the voltage on which the two inputs are centered. this results in the span of each input being cm v ref /2. this voltage has to be set up externally, and its range varies with v ref (see the driving the analog inputs section). the output coding is twos complement in fully differential mode with 1 lsb = 2 v ref /4096 or 2 2.5 v/4096 = 1.22 mv when v ref = 2.5 v. the output result is 11 bits, but this is shifted by one to the right. this allows the result in the adcdat mmr to be declared as a signed integer when writing c code. the designed code transitions occur midway between successive integer lsb values (that is, 1/2 lsb, 3/2 lsb, 5/2 lsb, , fs ? 3/2 lsb). the ideal input/output transfer characteristic is shown in figure 20 . 08675-014 output code voltage input (v in + ? v in ?) 0 1111 1111 1110 0 1111 1111 1100 0 1111 1111 1010 0 0000 0000 0010 0 0000 0000 0000 1 1111 1111 1110 1 0000 0000 0100 1 0000 0000 0010 1 0000 0000 0000 ?v ref + 1lsb +v ref ? 1lsb 0lsb 1lsb = 2 v ref 4096 sign bit figure 20. adc transfer function in differential mode
aduc7023 rev. b | page 29 of 96 typical operation when configured via the adc control and channel selection registers, the adc converts the analog input and provides a 12-bit result in the adc data register. the top four bits are the sign bits. the 12-bit result is placed from bit 16 to bit 27 as shown in figure 21 . note that in fully differential mode, the result is represented in twos complement format. in pseudo differential and single-ended modes, the result is represented in straight binary format. 08675-015 sign bits 12-bit adc result 31 27 16 15 0 figure 21. adc result format the same format is used in dacxdat, simplifying the software. current consumption the adc in standby mode, that is, powered up but not converting, typically consumes 640 a. the internal reference adds 140 a. during conversion, the extra current is 0.3 a multiplied by the sampling frequency (in khz). timing figure 22 gives details of the adc timing. users control the adc clock speed and the number of acquisition clocks in the adccon mmr. by default, the acquisition time is eight clocks, and the clock divider is two. the number of extra clocks (such as bit trial or write) is set to 19, which gives a sampling rate of 774 ksps. for conversion on the temperature sensor, set adccon = 0x37a3. when using multiple channels including the temperature sensor, the timing settings revert to the user- defined settings after reading the temperature sensor channel. 08675-016 adc clock a cq bit trial data adcsta = 0 adcsta = 1 adc interrupt write conv start adc busy adcdat figure 22. adc timing mmr interface the adc is controlled and configured via the eight mmrs described in this section. adccon register name: adccon address: 0xffff0500 default value: 0x0600 access: read/write function: adccon is an adc control register that allows the programmer to enable the adc peripheral, select the mode of operation of the adc (either in single- ended mode, pseudo differential mode, or fully differential mode), and select the conversion type. this mmr is described in table 24 . table 24. adccon mmr bit designations bit value description 15 to 14 reserved. 13 temperature sensor conversion enable. set to 1 for temperature sensor conversions. set to 0 for normal adc conversions. 12 to 10 adc clock speed. 000 f adc /1. this divider is provided to obtain 1 msps adc with an external clock <41.78 mhz. 001 f adc /2 (default value). 010 f adc /4. 011 f adc /8. 100 f adc /16. 101 f adc /32. 9 to 8 adc acquisition time. 00 2 clocks. 01 4 clocks. 10 8 clocks (default value). 11 16 clocks.
aduc7023 rev. b | page 30 of 96 bit value description 7 enable start conversion. this bit is set by the user to start any type of conversion command. this bit is cleared by the user to disable a start conversion (clearing this bit does not stop the adc when continuously converting). 6 enable the adc busy pin. this bit is set by the user to enable the adc busy pin. this bit is cleared by the user to disable the adc busy pin. 5 adc power control. this bit is set by the user to place the adc in normal mode (the adc must be powered up for at least 5 s before it converts correctly). this bit is cleared by the user to place the adc in power-down mode. 4 to 3 conversion mode. 00 single-ended mode. 01 differential mode. 10 pseudo differential mode. 11 reserved. 2 to 0 conversion type. 000 enable conv start pin as a conversion input. 001 enable timer1 as a conversion input. 010 enable timer0 as a conversion input. 011 single software conversion. this bit is set to 000 after conversion (note that bit 13 of the adccon mmr should be set before starting a single software conversion to avoid further conversions triggered by the conv start pin). 100 continuous software conversion. 101 pla conversion. other reserved. adccp register name: adccp address: 0xffff0504 default value: 0x00 access: read/write function: adccp is an adc positive channel selection register. this mmr is described in table 25 . table 25. adccp mmr bit designation bit value description 7 to 5 reserved. 4 to 0 positive channel selection bits. 00000 adc0. 00001 adc1. 00010 adc2. 00011 adc3. 00100 adc4 1 . 00101 adc5 1 . 00110 adc6 1 . 00111 adc7 1 . 01000 adc8 1 . 01001 adc9 1 . bit value description 01010 adc10 1 . 01011 reserved. 01100 adc12 1 . 01101 reserved 01110 dac1 01111 dac2. 10000 temperature sensor. 10001 agnd (self-diagnostic feature). 10010 internal reference (self-diagnostic feature). 10011 av dd /2. others reserved. 1 when a selected adc channel is shared with one gpio, by default, this pin is configured with a weak pull-up resistor enabled. the pull-u p resistor should be disabled manually in the appropriate gpxpar register. note the internal pull-up resistor on p2.0/ain12 for 40-lead package cannot be disabled.
aduc7023 rev. b | page 31 of 96 adccn register name: adccn address: 0xffff0508 default value: 0x01 access: read/write function: adccn is an adc negative channel selection register. this mmr is described in table 26 . table 26. adccn mmr bit designation bit value description 7 to 5 reserved. 4 to 0 negative channel selection bits. 00000 adc0. 00001 adc1. 00010 adc2. 00011 adc3. 00100 adc4. 00101 adc5. 00110 adc6. 00111 adc7. 01000 adc8. 01001 adc9. 01010 adc10. 01011 reserved 01100 adc12. 01101 reserved 01110 reserved 01111 dac1. 10000 temperature sensor. 10001 agnd (self-diagnostic feature). 10010 internal reference (self-diagnostic feature). 10011 reserved others reserved. adcsta register name: adcsta address: 0xffff050c default value: 0x00 access: read function: adcsta is an adc status register that indicates when an adc conversion result is ready. the adcsta register contains only one bit, adcready (bit 0), representing the status of the adc. this bit is set at the end of an adc conversion, generating an adc interrupt. it is cleared automatically by reading the adcdat mmr. when the adc is performing a conversion, the status of the adc can be read externally via the adc busy pin. this pin is high during a conversion. when the conversion is finished, adc busy goes back low. this information can be available on p0.0 (see the general-purpose input/output section) if enabled in the adccon register. adcdat register name: adcdat address: 0xffff0510 default value: 0x00000000 access: read function: adcdat is an adc data result register. hold the 12-bit adc result as shown in figure 21 . adcrst register name: adcrst address: 0xffff0514 default value: 0x00 access: read/write function: adcrst resets the digital interface of the adc. writing any value to this register resets all the adc registers to their default value.
aduc7023 rev. b | page 32 of 96 adcgn register name: adcgn address: 0xffff0530 default value: factory configured access: read/write function: adcgn is a 10-bit gain calibration register. adcof register name: adcof address: 0xffff0534 default value: factory configured access: read/write function: adcof is a 10-bit offset calibration register. converter operation the adc incorporates a successive approximation (sar) architecture involving a charge-sampled input stage. this architecture can operate in three different modes: differential, pseudo differential, and single-ended. differential mode the aduc7023 contains a successive approximation adc based on two capacitive dacs. figure 23 and figure 24 show simplified schematics of the adc in acquisition and conversion phase, respectively. the adc is comprised of control logic, a sar, and two capacitive dacs. in figure 23 (the acquisition phase), sw3 is closed and sw1 and sw2 are in position a. the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. 08675-017 capacitive dac capacitive dac control logic comparator sw3 sw1 a a b b sw2 c s c s v ref adc0 a dc11 mux channel+ channel? 08675-018 capacitive dac capacitive dac control logic comparator sw3 sw1 a a b b sw2 c s c s v ref adc0 a dc11 mux channel+ channel? figure 23. adc acquisition phase when the adc starts a conversion, as shown in figure 24 , sw3 opens, and then sw1 and sw2 move to position b. this causes the comparator to become unbalanced. both inputs are disconnected once the conversion begins. the control logic and the charge redistribution dacs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. the output impedances of the sources driving the v in+ and v inC pins must be matched; otherwise, the two inputs have different settling times, resulting in errors. 08675-019 capacitive dac capacitive dac control logic comparator sw3 sw1 a a b b sw2 c s c s v ref adc0 a dc11 v in? mux channel+ channel? figure 24. adc conversion phase pseudo differential mode in pseudo differential mode, channel? is linked to the v in? pin of the aduc7023 sw2 switches between a (channel?) and b (v ref ). v in? pin must be connected to ground or a low voltage. the input signal on v in+ can then vary from v in? to v ref + v in? . v in? must be chosen so that v ref + v in? does not exceed av dd . 08675-019 capacitive dac capacitive dac control logic comparator sw3 sw1 a a b b sw2 c s c s v ref ain0 ain11 v in? mux channel+ channel? figure 25. adc in pseudo differential mode
aduc7023 rev. b | page 33 of 96 single-ended mode in single-ended mode, sw2 is always connected internally to ground. the v in? pin can be floating. the input signal range on v in+ is 0 v to v ref . 08675-020 capacitive dac capacitive dac control logic comparator sw3 sw1 a b c s c s ain0 ain11 mux channel+ channel? figure 26. adc in single-ended mode analog input structure figure 27 shows the equivalent circuit of the analog input structure of the adc. the four diodes provide esd protection for the analog inputs. care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mv; this causes these diodes to become forward-biased and start conducting into the substrate. these diodes can conduct up to 10 ma without causing irreversible damage to the part. the c1 capacitors in figure 27 are typically 4 pf and can be primarily attributed to pin capacitance. the resistors are lumped components made up of the on resistance of the switches. the value of these resistors is typically about 100 . the c2 capacitors are the adc sampling capacitors and typically have a capacitance of 16 pf. a v dd c1 d d r1 c2 av dd c1 d d r1 c2 08675-021 figure 27. equivalent analog input circuit conversion phase: switches open, track phase: switches closed for ac applications, removing high frequency components from the analog input signal is recommended by using an rc low- pass filter on the relevant analog input pins. in applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc. this can necessitate the use of an input buffer amplifier. the choice of the op amp is a function of the particular application. figure 28 and figure 29 give an example of an adc front end. 08675-022 aduc7023 adc0 10? 0.01f figure 28. buffering single-e nded/pseudo differential input 08675-023 aduc7023 adc0 v ref adc1 figure 29. buffering differential inputs when no amplifier is used to drive the analog input, limit the source impedance to values lower than 1 k. the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. the thd increases as the source impedance increases and the performance degrades. driving the analog inputs internal or external references can be used for the adc. when operating in differential mode, there are restrictions on the common-mode input signal (v cm ), which is dependent upon the reference value and supply voltage used to ensure that the signal remains within the supply rails. table 27 gives some calculated v cm minimum and v cm maximum values. table 27. v cm ranges av dd v ref v cm min v cm max signal peak-to-peak 3.3 v 2.5 v 1.25 v 2.05 v 2.5 v 2.048 v 1.024 v 2.276 v 2.048 v 1.25 v 0.75 v 2.55 v 1.25 v 3.0 v 2.5 v 1.25 v 1.75 v 2.5 v 2.048 v 1.024 v 1.976 v 2.048 v 1.25 v 0.75 v 2.25 v 1.25 v calibration by default, the factory-set values written to the adc offset (adcof) and gain coefficient registers (adcgn) yield optimum performance in terms of endpoint errors and linearity for standalone operation of the part (see the specifications section). if system calibration is required, it is possible to modify the default offset and gain coefficients to improve endpoint errors, but note that any modification to the factory- set adcof and adcgn values can degrade adc linearity performance. for system offset error correction, the adc channel input stage must be tied to agnd. a continuous software adc conversion loop must be implemented by modifying the value in adcof until the adc result (adcdat) reads code 0 to code 1. if the adcdat value is greater than 1, adcof should be decremented until adcdat reads code 0 to code 1. offset error correction is done digitally and has a resolution of 0.25 lsb and a range of 3.125% of v ref .
aduc7023 rev. b | page 34 of 96 for system gain error correction, the adc channel input stage must be tied to v ref . a continuous software adc conversion loop must be implemented to modify the value in adcgn until the adcdat reads code 4094 to code 4095. if the adcdat value is less than 4094, adcgn should be incremented until adcdat reads code 4094 to code 4095. similar to the offset calibration, the gain calibration resolution is 0.25 lsb with a range of 3% of v ref . temperature sensor the aduc7023 provides a voltage output from an on-chip band gap reference that is proportional to absolute temperature. this voltage output can also be routed through the front-end adc multiplexer (effectively an additional adc channel input), facilitating an internal temperature sensor channel, measuring die temperature. an adc temperature sensor conversion differs from a standard adc voltage. the adc performance specifications do not apply to the temperature sensor. chopping of the internal amplifier should be enabled using the tscon register. to enable this mode, the user must set bit 0 of tscon. the user must also take two consecutive adc readings and average them in this mode. the adccon register must be configured to 0x37a3. to calculate die temperature use the following formula: t ? t ref = ( v adc ? v tref ) k where: t is the temperature result. t ref is 25c. v adc is the average adc result from two consecutive conversions. v tref is 1369 mv, which corresponds to t ref = 25c as described in table 1 . k is the gain of the adc in temperature sensor mode as determined by characterization data, k = 0.2262c/mv. this corresponds to 1/v tc specification as shown in table 1 . using the default values from table 1 and without any calibra- tion, this equation becomes t C 25c = ( v adc ? 1369) 0.2262 where: v adc is in millivolts. for increased accuracy, perform a single point calibration at a controlled temperature value. for the calculation shown without calibration, (t ref , v tref ) = (25c, 1369 mv). the idea of a single point calibration is to use other known (t ref , v tref ) values to replace the common (25c, 1369 mv) for every part. for some users, it is not possible to get such a known pair. for these cases, an aduc7023 comes with a single point calibration value loaded in the tempref register. for more details on this register, see the tempref register section. during production testing of the aduc7023, the tempref register is loaded with an offset adjustment factor. each part will have a different value in the tempref register. using this single point calibration, use the same formula as shown: t ? t ref = ( v adc ? v tref ) k where: t ref is 27c when using the tempref register method, but is not guaranteed. t tref can be calculated using the tempref register. tscon register name: tscon address: 0xffff0544 default value: 0x00 access: read/write table 28. tscon mmr bit designations bit description 7 to 1 reserved. 0 temperature sensor chop enable bit. this bit is set to 1 to enab le chopping of the internal amplifier to the adc. this bit is cleared to disable chopping. this bit is cleared by default. tempref register name: tempref address: 0xffff0548 default value: factory configured access: read/write
aduc7023 rev. b | page 35 of 96 table 29. tempref mmr bit designations bit description 15 to 9 reserved. 8 temperature reference voltage sign. 7 to 0 temperature sensor offset calibration voltage. to calculate the v tref from the tempref register, perform the following calculation: if tempref sign negative, subtract tempref from 2292 c tref = 2292 ? tempref [7:0] where temref [8] = 1. or if temref sign positive, add tempref to 2292 c tref = tempref [7:0] + 2292 where: tempref[8] = 0. then, v tref = ( c tref v ref )/4096 1000 where: c tref is calculated as above. v ref is 2.5 v, internal reference voltage. insert v tref into t C t ref = ( v adc C v tref ) k where: t ref is 27c, when using temref register. v adc is the average adc result from two consecutive conversions. v tref is calculated as above. note that adc code value 2292 is a default value when using the temref register. it is not an exact value and must only be used with the tempref register. band gap reference the aduc7023 provides an on-chip band gap reference of 2.5 v, which can be used for the adc and dac. this internal reference also appears on the v ref pin. when using the internal reference, a 0.47 f capacitor must be connected from the external v ref pin to agnd to ensure stability and fast response during adc conversions. this reference can also be connected to an external pin (v ref ) and used as a reference for other circuits in the system. an external buffer is required because of the low drive capability of the v ref output. a programmable option also allows an external reference input on the v ref pin. refcon register name: refcon address: 0xffff048c default value: 0x00 access: read/write function: the band gap reference interface consists of an 8-bit mmr refcon described in table 22 . table 22. refcon mmr bit designations bit description 7 to 2 reserved. 1 internal reference power-down bit. this bit is set to 1 to power down the internal reference source. this bit should be set when connecting an external reference source. this bit is cleared to enable the internal reference. this bit is cleared by default. 0 internal reference output enable. this bit is set by the user to connect the internal 2.5 v reference to the v ref pin. the reference can be used for an external component but needs to be buffered. this bit is cleared by the user to disconnect the reference from the v ref pin. to connect an external reference source to the aduc7023, configure refcon = 0x00. adc and the dacs can be configured to use the same or different reference resource. see table 41 .
aduc7023 rev. b | page 36 of 96 nonvolatile flash/ee memory the aduc7023 incorporates flash/ee memory technology on chip to provide the user with nonvolatile, in-circuit reprogram- mable memory space. like eeprom, flash memory can be programmed in-system at a byte level, although it must first be erased. the erase is performed in page blocks. as a result, flash memory is often and more correctly referred to as flash/ee memory. the flash/ee memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit programmability, high density, and low cost. incorporated in the aduc7023, flash/ee memory technology allows the user to update program code space in-circuit, without needing to replace one-time programmable (otp) devices at remote operating nodes. each part contains a 64 kb array of flash/ee memory. the lower 62 kb are available to the user, and the upper 2 kb contain permanently embedded firmware, allowing in-circuit serial download. these 2 kb of embedded firmware also contain a power-on configuration routine that downloads factory- calibrated coefficients to the various calibrated peripherals (such as adc, temperature sensor, and band gap references). this 2 kb embedded firmware is hidden from user code. flash/ee memory reliability th e flash/ee memory arrays on the parts are fully qualified for two key flash/ee memory characteristics: flash/ee memory cycling endurance and flash/ee memory data retention. en durance quantifies the ability of the flash/ee memory to be cycled through many program, read, and erase cycles. a single endurance cycle is composed of four independent, sequential events, defined as: 1. initial page erase sequence. 2. read/verify sequence (single flash/ee). 3. byte program sequence memory. 4. second read/verify sequence (endurance cycle). in reliability qualification, every half word (16-bit wide) location of the three pages (top, middle, and bottom) in the flash/ee memory is cycled 10,000 times from 0x0000 to 0xffff. as indicated in table 1 , the flash/ee memory endurance qualification is carried out in accordance with jedec retention lifetime specification a117 over the industrial temperature range of ?40 to +125c. the results allow the specification of a minimum endurance figure over a supply temperature of 10,000 cycles. retention quantifies the ability of the flash/ee memory to retain its programmed data over time. again, the parts are qualified in accordance with the formal jedec retention lifetime specification (a117) at a specific junction temperature (t j = 85c). as part of this qualification procedure, the flash/ee memory is cycled to its specified endurance limit before data retention is characterized. this means that the flash/ee memory is guaranteed to retain its data for its fully specified retention lifetime every time the flash/ee memory is reprogrammed. in addition, note that retention lifetime, based on activation energy of 0.6 ev, derates with t j as shown in figure 30 . 150 300 450 600 30 40 55 70 85 100 125 135 150 retention (years) 0 08675-024 junction temperature (c) figure 30. flash/ee memory data retention programming the 62 kb of flash/ee memory can be programmed in circuit, using the serial download mode or the provided jtag mode. downloading (in-circuit programming) via i 2 c the aduc7023 facilitates code download via the the i 2 c port. the parts enter download mode after a reset or power cycle if the bm pin is pulled low through an external 1 k resistor and flash addess 0x80014 = 0xffffffff. once in download mode, the user can download code to the full 62 kb of flash/ee memory while the device is in-circuit in its target application hardware. an executable pc i 2 c download is provided as part of the development system for serial downloading via the i 2 c. a usb to i 2 c download dongle can be purchased from analog devices, inc. this board connects to the usb port of a pc and to the i 2 c port of the aduc7023. the part number is usb- i2c/lin-conv-z. the an-806 application note describes the protocol for serial downloading via the i 2 c in more detail. jtag access the jtag protocol uses the on-chip jtag interface to facilitate code download and debug. to access the part via the jtag interface, the p0.0/bm pin must be set high to enable p0.1/p0.2/p0.3 as jtag pins. when debugging, user code should not write to the p0.1/p0.2 and p0.3 pins. if user code toggles any of these pins, jtag debug pods are not able to connect to the aduc7023. in case this happens, the user should ensure that flash address 0x80014 is erased to allow erasing of the part through the i 2 c interface.
aduc7023 rev. b | page 37 of 96 security the 62 kb of flash/ee memory available to the user can be read and write protected. bit 31 of the feepro/feehide mmr (see table 33 ) protects the 62 kb from being read through jtag programming mode. the other 31 bits of this register protect writing to the flash memory. each bit protects four pages, that is, 2 kb. write protection is activated for all types of access. three levels of protection protection can be set and removed by writing directly into feehide mmr. this protection does not remain after reset. protection can be set by writing into feepro mmr. it only takes effect after a save protection command (0x0c) and a reset. the feepro mmr is protected by a key to avoid direct access. the key is saved once and must be entered again to modify feepro. a mass erase sets the key back to 0xffff but also erases all the user code. fl ash can be permanently protected by using the feepro mmr and a particular value of key: 0xdeaddead. entering the key again to modify the feepro register is not allowed. se quence to write the key 1. write the bit in feepro corresponding to the page to be protected. 2. enable key protection by setting bit 6 of feemod (bit 5 must equal 0). 3. write a 32-bit key in feeadr, feedat. 4. run the write key command 0x0c in feecon; wait for the read to be successful by monitoring feesta. 5. reset the part. to remove or modify the protection, the same sequence is used with a modified value of feepro. if the key chosen is the value 0xdead, the memory protection cannot be removed. only a mass erase unprotects the part, but it also erases all user code. the sequence to write the key is illustrated in the following example (this protects writing page 4 to page 7 of the flash): feepro=0xfffffffd; //protect page 4 to page 7 feemod=0x48; //write key enable feeadr=0x1234; //16 bit key value feedat=0x5678; //16 bit key value feecon= 0x0c; //write key command the same sequence should be followed to protect the part permanently with feeadr = 0xdead and feedat = 0xdead . flash/ee control interface serial and jtag programming use the flash/ee control interface, which includes the eight mmrs outlined in this section. feesta register name: feesta address: 0xfffff800 default value: 0x20 access: read function: feesta is a read-only register that reflects the status of the flash control interface as described in table 30 . table 30. feesta mmr bit designations bit description 7 to 6 reserved. 5 reserved. 4 reserved. 3 flash interrupt status bit. this bit is set automatically when an inte rrupt occurs, that is, when a command is co mplete and the flash/ee interrupt enable b it in the feemod register is set. this bit is cleared when reading feesta register. 2 flash/ee controller busy. this bit is set automatically when the controller is busy. this bit is cleared automatically when the controller is not busy. 1 command fail. this bit is set automatically when a command is not completed. this bit is cleared automatically when reading feesta register. 0 command pass. this bit is set by the microconverter when a command is completed. this bit is cleared automatically when reading the feesta register.
aduc7023 rev. b | page 38 of 96 feemod register name: feemod address: 0xfffff804 default value: 0x0000 access: read/write function: feemod sets the operating mode of the flash control interface. table 31 shows feemod mmr bit designations. table 31. feemod mmr bit designations bit description 15 to 9 reserved. 8 reserved. always set this bit to 0. 7 to 5 reserved. always set this bit to 0 except when writing keys. see the sequence to write the key section. 4 flash/ee interrupt enable. this bit is set by the user to enab le the flash/ee interrupt. the interrup t occurs when a command is complete. this bit is cleared by the user to disable the flash/ee interrupt. 3 erase/write command protection. this bit is set by the user to enable the erase and write commands. this bit is cleared to protect th e flash/ee against erase/write command. 2 to 0 reserved. always set this bit to 0. feecon register name: feecon address: 0xfffff808 default value: 0x07 access: read/write function: feecon is an 8-bit command register. the commands are described in table 32 . table 32. command codes in feecon code command description 0x00 1 null idle state. 0x01 1 single read load feedat with the 16-bit data. indexed by feeadr. 0x02 1 single write write feedat at the address pointed by feeadr. this operation takes 50 s. 0x03 1 erase/write erase the page indexed by feeadr, and write feedat at the location pointed by feeadr. this operation takes approximately 24 ms. 0x04 1 single verify compare the contents of the location pointed by feeadr to the data in feed at. the result of the comparison is returned in feesta bit 1. 0x05 1 single erase erase the page indexed by feeadr. 0x06 1 mass erase erase 62 kb of user space. the 2 kb of kernel are protec ted. this operation takes 2.48 sec. to prevent accidental execution, a command sequence is required to execute this instruction. see the command sequence for executing a mass erase section. 0x07 reserved reserved. 0x08 reserved reserved. 0x09 reserved reserved. 0x0a reserved reserved. 0x0b signature give a signature of the 64 kb of flash/ee in th e 24-bit feesign mmr. this operation takes 32,778 clock cycles. 0x0c protect this command can run one time only. the value of feepro is saved and removed only with a mass erase (0x06) or the key (feeadr/feedat).
aduc7023 rev. b | page 39 of 96 code command description 0x0d reserved reserved. 0x0e reserved reserved. 0x0f ping no operation; interrupt generated. 1 the feecon register always reads 0x07 immediat ely after execution of any of these commands. feedat register name feedat address 0xfffff0c default value 0xxxxx access read/write function feedat is a 1-bit data register feeadr register name feeadr address 0xfffff10 default value 0x0000 access read/write function feeadr is another 1-bit address register feesign register name feesign address 0xfffff1 default value 0xffffff access read function feesign is a 24-bit code signature feepro register name feepro address 0xfffff1c default value 0x00000000 access read/write function feepro mmr provides protection following a subsequent reset of the mmr it requires a software key (see table 33 ) feehide register name feehide address 0xfffff20 default value 0xffffffff access read/write function feehide mmr provides immediate protection it does not require any software key the protection settings in feehide are cleared by a reset (see table 33 ) table 33. feepro and feehide mmr bit designations bit description 31 read protection. this bit is cleared by the user to protect the code this bit is set by the user to allow reading the code. 30 to 0 write protection for page 123 to page 120, page 119 to page 116, and page 0 to page 3. this bit is cleared by the user to protect the pages in writing. this bit is set by the user to allow writing the pages. command sequence for executing a mass erase feedat = 0x3cff; feeadr = 0xffc3; feemod = feemod|0x8; //erase key enable feecon = 0x06; //mass erase command
aduc7023 rev. b | page 40 of 96 execution time from sram and flash/ee execution from sram fetching instructions from sram takes one clock cycle because the access time of the sram is 2 ns, and a clock cycle is 22 ns minimum however, if the instruction involves reading or writing data to memory, one extra cycle must be added if the data is in sram (or three cycles if the data is in flash/ee) one cycle to execute the instruction and two cycles to obtain the 32-bit data from flash/ee a control flow instruction (a branch instruction, for example) takes one cycle to fetch but also takes two cycles to fill the pipeline with the new instructions execution from flash/ee because the flash/ee width is 1 bits and the access time for 1-bit words is 22 ns, execution from flash/ee cannot be completed in one cycle (as can be done from sram when the cd bit 0) also, some dead times are needed before accessing data for any value of cd bits in arm mode, where instructions are 32 bits, two cycles are needed to fetch any instruction when cd 0 in thumb mode, where instructions are 1 bits, one cycle is needed to fetch any instruction timing is identical in both modes when executing instructions that involve using the flash/ee for data memory if the instruction to be executed is a control flow instruction, an extra cycle is needed to decode the new address of the program counter, and then four cycles are needed to fill the pipeline a data processing instruction involving only the core register does not require any extra clock cycles however, if it involves data in flash/ee, an extra clock cycle is needed to decode the address of the data, and two cycles are needed to get the 32-bit data from flash/ee an extra cycle must also be added before fetching another instruction data transfer instructions are more complex and are summaried in table 34 table 34. execution cycles in arm/thumb mode instructions fetch cycles dead time data access dead time ld 1 2/1 1 2 1 ldh 2/1 1 1 1 ldm/push 2/1 n 2 2 n 2 n 1 str 1 2/1 1 2 20 ns 1 strh 2/1 1 20 ns 1 strm/pop 2/1 n 1 2 n 20 ns 1 n 1 1 the swap instruction combines an ld and str instruction with only one fetch, giving a total of eight cycles + 40 ns. 2 n is the number of data to load or store in the multiple load/store instruction (1 < n 16). reset and remap the arm exception vectors are all situated at the bottom of the memory array, from address 0x00000000 to address 0x00000020 as shown in figure 31 . 08675-025 kernel interrupt service routines interrupt service routines arm exception vector addresses 0x00000020 0x00011fff 0x0008ffff 0xffffffff flash/ee sram mirror space 0x00000000 0x00000000 0x00010000 0x00080000 figure 31. remap for exception execution by default, and after any reset, the flash/ee is mirrored at the bottom of the memory array. the remap function allows the programmer to mirror the sram at the bottom of the memory array, which facilitates execution of exception routines from sram instead of from flash/ee. this means exceptions are executed twice as fast, being executed in 32-bit arm mode with 32-bit wide sram instead of 16-bit wide flash/ee memory. remap operation when a reset occurs on the aduc023, execution automatically starts in factory programmed, internal configuration code this kernel is hidden and cannot be accessed by user code if the part is in normal mode (bm pin is high), it executes the power-on configuration routine of the kernel and then umps to the reset vector address, 0x00000000, to execute the reset exception routine of the user because the flash/ee is mirrored at the bottom of the memory array at reset, the reset interrupt routine must always be written in flash/ee the remap is done from flash/ee by setting bit 0 of the remap register caution must be taken to execute this command from flash/ee above address 0x0000020, and not from the bottom of the array because this is replaced by the sram this operation is reversible the flash/ee can be remapped at address 0x00000000 by clearing bit 0 of the remap mmr caution must again be taken to execute the remap function from outside the mirrored area any type of reset remaps the flash/ee memory at the bottom of the array
aduc7023 rev. b | page 41 of 96 remap register name: remap address: 0xffff0220 default value: 0x00 access: read/write table 35. remap mmr bit designations bit name description 7 to 5 reserved. 4 read-only bit. indicates the size of the flash/ee memory available. if this bit is set, only 32 kb of flash/ee memory is available. 3 read-only bit. indicates the size of the sram memory available. if this bit is set, only 4 kb of sram is available. 2 to 1 jtafo read only bits. see the p0.0/bm description for further details. if = [00], then p0.1/p0.2/p0.3 are configured as jtag pins. if = [1x], then p0.1/p0.2/p0.3 are configured as gpio pins. these bits are configured by the kernel after any reset sequence and depend on the state of p0.0 during the last reset sequence. 0 remap remap bit. this bit is set by the user to remap the sram to address 0x00000000. this bit is cleared automatically after reset to remap the flash/ee memory to address 0x00000000. reset operation there are four kinds of reset: external, power-on, watchdog expiration, and software force. the rststa register indicates the source of the last reset, and rstclr allows clearing of the rststa register. these registers can be used during a reset exception service routine to identify the source of the reset. if rststa is null, the reset is external. the rstcfg register allows different peripherals to retain their state after a watchdog or software reset. rststa register name: rststa address: 0xffff0230 default value: 0x01 access: read/write table 36. rststa mmr bit designations bit description 7 to 3 reserved. 2 software reset. this bit is set by the user to force a software reset. this bit is cleared by setting the corresponding bit in rstclr. 1 watchdog timeout. this bit is set automatically when a watchdog timeout occurs. this bit is cleared by setting the corresponding bit in rstclr. 0 power-on reset. this bit is set automatically when a power-on reset occurs. this bit is cleared by setting the corresponding bit in rstclr. rstclr register name: rstclr address: 0xffff0234 default value: 0x00 access: write function: note that to clear the rststa register, users must write the value 0x07 to the rstclr register. rstcfg register name: rstcfg address: 0xffff024c default value: 0x00 access: read/write table 37. rstcfg mmr bit designations bit description 7 to 3 reserved. always set to 0. 2 this bit is set to 1 to config ure the dac outputs to retain their state after a watchdog or software reset. this bit is cleared for the dac pins and registers to return to their default state. 1 reserved. always set to 0. 0 this bit is set to 1 to configure the gpio pins to retain their state after a watchdog or software reset. this bit is cleared for the gpio pins and registers to return to their default state.
aduc7023 rev. b | page 42 of 96 rstkey1 register name: rstkey1 address: 0xffff0248 default value: 0xxx access write rstkey2register name: rstkey2 address: 0xffff0250 default value: 0xxx access: write table 38. rstcfg write sequence name code rstkey1 0x76 rstcfg user value rstkey2 0xb1
aduc7023 rev. b | page 43 of 96 other analog peripherals dac the aduc7023 incorporates four, 12-bit voltage output dacs on chip. each dac has a rail-to-rail voltage output buffer capable of driving 5 k/100 pf. each dac has two selectable ranges: 0 v to v ref (internal band gap 2.5 v reference) and 0 v to av dd . the signal range is 0 v to av dd . by setting rstcfg bit 2, the dac output pins can retain their state during a watchdog or software reset. mmrs interface each dac is independently configurable through a control register and a data register. these two registers are identical for the four dacs. only dac0con (see table 39 ) and dac0dat (see table 40 ) are described in detail in this section. dacxcon registers name address default value access dac0con 0xffff0600 0x00 r/w dac1con 0xffff0608 0x00 r/w dac2con 0xffff0610 0x00 r/w dac3con 0xffff0618 0x00 r/w table 39. dac0con mmr bit designations bit value name description 7 reserved. 6 dacby this bit is set to bypass the dac output buffer. this bit is cleared to enable the dac output buffer. 5 dacclk dac update rate. this bit is set by the user to update the dac using timer1. this bit is cleared by the user to update the dac using hclk (core clock). 4 dacclr dac clear bit. this bit is set by the user to enable normal dac operation. this bit is cleared by the user to reset data register of the dac to 0. 3 reserved. this bit remains at 0. 2 reserved. this bit remains at 0. 1 to 0 dac range bits. 00 power-down mode. the dac output is in tristate. 01 reserved. 10 0 v to v ref (2.5 v) range. 11 0 v to av dd range. dacxdat registers name address default value access dac0dat 0xffff0604 0x00000000 r/w dac1dat 0xffff060c 0x00000000 r/w dac2dat 0xffff0614 0x00000000 r/w dac3dat 0xffff061c 0x00000000 r/w table 40. dac0dat mmr bit designations bit description 31 to 28 reserved. 27 to 16 12-bit data for dac0. 15 to 0 reserved. using the dacs the on-chip dac architecture consists of a resistor string dac followed by an output buffer ampl ifier. the functional equivalent is shown in figure 32 . 08675-026 r r r r r dac0 v ref av dd dac ref figure 32. dac structure as illustrated in figure 32 , the reference source for each dac is user-selectable in software. it can be either av dd or v ref . in 0-to-av dd mode, the dac output transfer function spans from 0 v to the voltage at the av dd pin. in 0-to-v ref mode, the dac output transfer function spans from 0 v to the internal 2.5 v reference, v ref . the dac output buffer amplifier features a true, rail-to-rail output stage implementation. this means that when unloaded, each output is capable of swinging to within less than 5 mv of both av dd and ground. moreover, the dac linearity specification (when driving a 5 k resistive load to ground) is guaranteed through the full transfer function except code 0 to code 100, and, in 0-to-av dd mode only, code 3995 to code 4095. linearity degradation near ground and v dd is caused by satu- ration of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in figure 33 . the dotted line in figure 33 indicates the ideal transfer function, and the solid line represents what the transfer function may look like with endpoint nonlinearities due to saturation of the output amplifier. figure 33 represents a transfer function in 0-to-
aduc7023 rev. b | page 44 of 96 av dd mode only. in 0-to-v ref mode (with v ref < av dd ), the lower nonlinearity is similar. however, the upper portion of the transfer function follows the ideal line right to the end (v ref in this case, not av dd ), showing no signs of endpoint linearity errors. 08675-027 av dd av dd ? 100mv 100mv 0x00000000 0x0fff0000 figure 33. endpoint nonlineariti es due to amplifier saturation the endpoint nonlinearities conceptually illustrated in figure 33 get worse as a function of output loading. most of the aduc7023 data sheet specifications assume a 5 k resistive load to ground at the dac output. as the output is forced to source or sink more current, the nonlinear regions at the top or bottom of figure 33 become larger, respectively. with larger current demands, this can significantly limit output voltage swing. references to adc and the dacs adc and dacs can be configured to use internal v ref or an external reference as a reference source. internal v ref must work with an external 0.47 f capacitor. table 41. reference source selection for adc and dac refcon bit 0 dacxcon1:0 description 0 00 adc works with external reference. dacs power down. 0 01 reserved. 0 10 reserved. 0 11 adc works with external reference. dacs work with internal av dd . 1 00 adc works with internal v ref . dacs power down. 1 01 adc and dacs work with an external reference. the external reference must be capable of overdriving the internal reference. 1 10 adc and dacs work with internal v ref . 1 11 adc works with internal v ref . dacs work with internal av dd . configuring dac buffers in op amp mode in op amp mode, the dac output buffers are used as an op amp with the dac itself disabled. if dacbcfg bit 0 is set, adc0 is the positive input to the op amp, adc1 is the negative input, and dac0 is the output. in this mode, the dac should be powered down by clearing bit 0 and bit 1 of dac0con. if dacbcfg bit 1 is set, adc2 is the positive input to the op amp, adc3 is the negative input, and dac1 is the output. in this mode, the dac should be powered down by clearing bit 0 and bit 1 of dac1con. if dacbcfg bit 2 is set, adc4 is the positive input to the op amp, adc5 is the negative input, and dac2 is the output. in this mode, the dac should be powered down by clearing bit 0 and bit 1 of dac2con. if dacbcfg bit 3 is set, adc8 is the positive input to the op amp, adc9 is the negative input, and dac3 is the output. in this mode, the dac should be powered down by clearing bit 0 and bit 1 of dac3con. dacbcfg register name: dacbcfg address: 0xffff0654 default value: 0x00 access: read/write table 42. dacbcfg mmr bit designations bit description 7 to 4 reserved. always set to 0. 3 this bit is set to 1 to configure dac3 output buffer in op amp mode. this bit is cleared for the dac buffer to operate as normal. 2 this bit is set to 1 to configure dac2 output buffer in op amp mode. this bit is cleared for the dac buffer to operate as normal. 1 this bit is set to 1 to configure dac1 output buffer in op amp mode. this bit is cleared for the dac buffer to operate as normal. 0 this bit is set to 1 to configure dac0 output buffer in op amp mode. this bit is cleared for the dac buffer to operate as normal.
aduc7023 rev. b | page 45 of 96 dacbkey0 register name: dacbkey0 address: 0xffff0650 default value: 0x0000 access: write dacbkey1 register name: dacbkey1 address: 0xffff0658 default value: 0x0000 access: write table 43. dacbcfg write sequence name code dacbkey0 0x9a dacbcfg user value dacbkey1 0x0c power supply monitor the power supply monitor regulates the iov dd supply on the aduc7023. it indicates when the iov dd supply pin drops below a supply trip point. the monitor function is controlled via the psmcon register. if enabled in the irqen or fiqen register, the monitor interrupts the core using the psmi bit in the psmcon mmr. this bit is immediately cleared when cmp goes high. this monitor function allows the user to save working registers to avoid possible data loss due to low supply or brownout conditions. it also ensures that normal code execution does not resume until a safe supply level has been established. psmcon register name: psmcon address: 0xffff0440 default value: 0x0008 access: read/write table 44. psmcon mmr bit descriptions bit name description 3 cmp comparator bit. this is a read-only bit that directly reflects the state of the comparator. read 1 indicates the iov dd supply is above its selected trip point, or the psm is in power-down mode. read 0 indicates the iov dd supply is below its selected trip point. this bit should be set before leaving the interrupt service routine. 2 tp trip point selection bits. 0 = 2.79 v. 1 = reserved. 1 psmen power supply monitor enable bit. this bit is set to 1 to enable the power supply monitor circuit. this bit is cleared to 0 to disable the power supply monitor circuit. 0 psmi power supply monitor interrupt bit. this bit is set high by the microconverter once cmp goes low, indicating low i/o supply. the psmi bit can be used to interrupt the processor. once cmp returns high, the psmi bit can be cleared by writing a 1 to this location. a 0 write has no effect. there is no timeout delay; psmi can be immediately cleared once cmp goes high. comparator the aduc7023 integrates voltage comparators. the positive input is multiplexed with adc2, and the negative input has two options: adc3 or dac0. the output of the comparator can be configured to generate a system interrupt, be routed directly to the programmable logic array, start an adc conversion, or be on an external pin, comp out , as shown in figure 34 . 08675-028 mux irq mux dac0 adc2/cmp0 adc3/cmp1 p0.5/comp out figure 34. comparator hysteresis figure 35 shows how the input offset voltage and hysteresis terms are defined. input offset voltage (v os ) is the difference between the center of the hysteresis range and the ground level. this can either be positive or negative. the hysteresis voltage (v h ) is ? the width of the hysteresis range. comp out cmp0 v h v h v os 08675-029 figure 35. comparator hysteresis transfer function
aduc7023 rev. b | page 46 of 96 comparator interface the comparator interface consists of a 16-bit mmr, cmpcon, which is described in table 45 . cmpcon register name: cmpcon address: 0xffff0444 default value: 0x0000 access: read/write table 45. cmpcon mmr bit descriptions bit value name description 15 to 11 reserved. 10 cmpen comparator enable bit. this bit is set by the user to enable the comparator. this bit is cleared by the user to disable the comparator. 9 to 8 cmpin comparator negative input select bits. 00 av dd /2. 01 adc3 input. 10 dac0 output. 11 reserved. 7 to 6 cmpoc comparator output configuration bits. 00 reserved. 01 reserved. 10 output on comp out . 11 irq. 5 cmpol comparator output logic state bit. when low, the comp arator output is high if the positive input (cmp0) is above the negative input (cmp1). when high, the comparator output is high if the positive input is below the negative input. 4 to 3 cmpres response time. 00 5 s response time typical for large signals (2.5 v differential). 17 s response time typical for small signals (0.65 mv differential). 11 3 s typical. 01/10 reserved. 2 cmphyst comparator hysteresis bit. this bit is set by the user to have a hysteresis of about 7.5 mv. this bit is cleared by the user to have no hysteresis. 1 cmpori comparator output rising edge interrupt. this bit is set automatically when a rising edge occurs on the monitored voltage (cmp0). this bit is cleared by the user by writing a 1 to this bit. 0 cmpofi comparator output rallying edge interrupt. this bit is set automatically when a falling edge occurs on the monitored voltage (cmp0). this bit is cleared by user.
aduc7023 rev. b | page 47 of 96 oscillator and pllpower control clocking system each aduc023 integrates a 32 kh 3 oscillator, a clock divider, and a pll the pll locks onto a multiple (12) of the internal oscillator or an external 32 kh crystal to provide a stable 41 mh clock (uclk) for the system to allow power saving, the core can operate at this frequency, or at binary submultiples of it the actual core operating frequency, uclk/2 cd , is referred to as hclk the default core clock is the pll clock divided by (cd 3) or 22 mh the core clock frequency can also come from an external clock on the eclk pin as described in figure 3 08675-030 *32.768khz 3% at power up 41.78mhz oclk 32.768khz watchdog timer internal 32khz* oscillator crystal oscillator timers mdclk hclk pll core i 2 c uclk analog peripherals /2 cd cd xclko xclki p1.2/xclk p1.2/eclk figure 36. clocking system the selection of the clock source is in the pllcon register. by default, the part uses the internal oscillator feeding the pll. in noisy environments, noise can couple to the external crystal pins, and pll may quickly lose lock. a pll interrupt is provided in the interrupt controller. the core clock is immediately halted, and this interrupt is only serviced when the lock is restored. in case of crystal loss, use the watchdog timer. during initialization, a test on the rststa can determine if the reset came from the watchdog timer. power control system a choice of operating modes is available on the aduc023 table 4 describes what part is powered on in the different modes and indicates the power-up time table 4 gives some typical values of the total current consumption (analog digital supply currents) in the different modes, depending on the clock divider bits the adc is turned off note that these values also include current consumption of the regulator and other parts on the test board where these values are measured table 4 operating modes mode core peripherals pll xtal/t2/t3 irq0 to irq3 start-up/power-on time active yes x x x x 66 ms at cd = 0 pause x x x x 230 ns at cd = 0; 3 s at cd = 7 nap x x x 283 ns at cd = 0; 3 s at cd = 7 sleep x x 1.23 ms stop x 1.45 ms x = dont care. table 47. typical current consumption at 25c in ma pc[2:0] mode cd = 0 cd = 1 cd = 2 cd = 3 cd = 4 cd = 5 cd = 6 cd = 7 000 active 28 17 12 11 9.3 7.5 7.2 7 001 pause 14 9 7.6 5.7 4.8 4.6 4.6 4.6 010 nap 5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 011 sleep 0.23 0.23 0.23 0.23 0.23 0.23 0.23 0.23 100 stop 0.23 0.23 0.23 0.23 0.23 0.23 0.23 0.23
aduc7023 rev. b | page 48 of 96 mmrs and keys the operating mode, clocking mode, and programmable clock divider are controlled via three mmrs, pllcon (see table 48 ) and powconx. pllcon controls the operating mode of the clock system, powcon0 controls the core clock frequency and the power-down mode, powcon1 controls the clock frequency to i 2 c and spi. to prevent accidental programming, a certain sequence has to be followed to write to the pllcon and powconx registers. pllkey1 register name: pllkey1 address: 0xffff0410 default value: 0xxxxx access: write pllkey2 register name: pllkey2 address: 0xffff0418 default value: 0xxxxx access: write pllcon register name: pllcon address: 0xffff0414 default value: 0x21 access: read/write table 48. pllcon mmr bit designations bit value name description 7 to 6 reserved. 5 osel 32 khz pll input selection. this bit is set by the user to select the internal 32 khz oscillator. this bit is set by default. this bit is cleared by the user to select the external 32 khz crystal. 4 to 2 reserved. 1 to 0 mdclk clocking modes. 00 reserved. 01 pll default configuration. 10 reserved. 11 external clock on pin 33 (40-lfcsp lead)/pin 25 (32-lfcsp lead). table 49. pllcon write sequence name code pllkey1 0xaa pllcon user value pllkey2 0x55 powkey1 register name: powkey1 address: 0xffff0404 default value: 0xxxxx access: write function: powkey1 prevents accidental programming to powcon0. powkey2 register name powkey2 address 0xffff040c default value 0xxxxx access write function: powkey2 prevents accidental programming to powcon0. powcon0 register name: powcon0 address: 0xffff0408 default value: 0x00 access: read/write table 50. powcon0 mmr bit designations bit value name description 7 reserved. 6 to 4 pc operating modes. 000 active mode. 001 pause mode. 010 nap. 011 sleep mode. irq0 to irq3 can wake up the part. 100 stop mode. irq0 to irq3 can wake up the part. others reserved. 3 reserved.
aduc7023 rev. b | page 49 of 96 bit value name description 2 to 0 cd cpu clock divider bits. 000 41.78 mhz. 001 20.89 mhz. 010 10.44 mhz. 011 5.22 mhz. 100 2.61 mhz. 101 1.31 mhz. 110 653 khz. 111 326 khz. table 51. powcon0 write sequence name code powkey1 0x01 powcon0 user value powkey2 0xf4 powkey3 register name: powkey3 address: 0xffff0434 default value: 0xxxxx access: write function: powkey3 prevents accidental programming to powcon1. powkey4 register name powkey4 address 0xffff043c default value 0xxxxx access write function: powkey4 prevents accidental programming to powcon1. powcon1 register name: powcon1 address: 0xffff0438 default value: 0x0004 access: read/write table 52. powcon1 mmr bit designations bit value name description 15 to 9 reserved. 8 spipo clearing this bit powers down the spi. 7 to 6 spiclkdiv spi block driving clock divider bits. 00 41.78 mhz. 01 20.89 mhz. 10 10.44 mhz. 11 5.22 mhz. 5 i2c1po clearing this bit powers down the i 2 c1. 4 to 3 i2c1clkdiv i 2 c0 block driving clock divider bits. 00 41.78 mhz. 01 10.44 mhz. 10 5.22 mhz. 11 1.31 mhz. 2 i2c0po clearing this bit powers down the i 2 c0. 1 to 0 i2c0clkdiv i 2 c1 block driving clock divider bits. 00 41.78 mhz. 01 10.44 mhz. 10 5.22 mhz. 11 1.31 mhz. table 53. powcon1 write sequence name code powkey3 0x76 powcon1 user value powkey4 0xb1
aduc7023 rev. b | page 50 of 96 digital peripherals general-purpose input/output the aduc7023 provides up to 20 general-purpose, bidirectional i/o (gpio) pins. all i/o pins are 5 v tolerant, meaning the gpios support an input voltage of 5 v. in general, many of the gpio pins have multiple functions (see table 54 for the pin function definitions). by default, the gpio pins are configured in gpio mode. all gpio pins have an internal pull-up resistor (of about 100 k) and their drive capability is 1.6 ma. note that a maximum of 20 gpios can drive 1.6 ma at the same time. using the gpxpar registers, it is possible to enable/disable the pull-up resistors. the 20 gpios are grouped in three ports, port 0 to port 2 (port x). each port is controlled by four or five mmrs. the input level of any gpio can be read at any time in the gpxdat mmr, even when the pin is configured in a mode other than gpio. the pla input is always active. when the aduc7023 part enters a power-saving mode, the gpio pins retain their state. also note, that by setting rstcfg bit 0, the gpio pins can retain their state during a watchdog or software reset. table 54. gpio pin function descriptions configuration port pin 00 01 10 11 0 p0.0 gpio/bm ntrst adc busy plai[8] p0.1 1 gpio tdo plai[9] p0.2 1 gpio tdi plao[8] p0.3 1 gpio tck plao[9] p0.4 gpio/irq0 scl0 conv start plai[0] p0.5 gpio sda0 comp out plai[1] p0.6 gpio miso scl1 2 plai[2] p0.7 gpio mosi sda1 2 plao[0] 1 p1.0 gpio sclk pwm0 plao[1] p1.1 gpio/irq1 ss pwm1 plao[2] p1.2 3 gpio/irq2 adc4 eclk plai[3] p1.3 gpio/irq3 adc5 plai[4] p1.4 gpio adc10 plao[3] p1.5 gpio adc6 pwm tripinput plao[4] p1.6 gpio scl1 4 pwm2 plai[5] p1.7 gpio sda1 4 pwm3 plai[6] 2 p2.0 gpio adc12 pwm4 plai[7] p2.2 gpio adc7 pwmsync plao[6] p2.3 gpio adc8 plao[7] p2.4 gpio adc9 plai[10] 1 these pins should not be used by us er code when debugging the part via jtag. see table 30 and the remap register for further details on how to configure these pins for gpio mode. th e default value of these pins depends on the level of the p0.0/bm pin during the last reset sequence. 2 i 2 c1 function is only available on the 32-lead package. 3 when configured in mode 2, p1.2 is eclk by default, or core clock output. to configure it as a clock input, the mdcl k bits in pllcon must be set to 11. 4 i 2 c1 function is only available on the 40-lead package. gpxcon registers name address default value access gp0con 0xfffff400 0x00001111 r/w gp1con 0xfffff404 0x00000000 r/w gp2con 0xfffff408 0x00000000 r/w gpxcon are the port x control registers, which select the function of each pin of port x as described in table 55 . table 55. gpxcon mmr bit descriptions bit description 31 to 30 reserved. 29 to 28 select function of px.7 pin. 27 to 26 reserved. 25 to 24 select function of px.6 pin. 23 to 22 reserved. 21 to 20 select function of px.5 pin. 19 to 18 reserved. 17 to 16 select function of px.4 pin. 15 to 14 reserved. 13 to 12 select function of px.3 pin. 11 to 10 reserved. 9 to 8 select function of px.2 pin. 7 to 6 reserved. 5 to 4 select function of px.1 pin. 3 to 2 reserved. 1 to 0 select function of px.0 pin. gp0par register name gp0par address 0xfffff42c default value 0x22220000 access read/write function gp0par programs the parameters for port 0, port 1, and port 2. note that the gp0dat mmr must always be written after changing the gp0par mmr. gp1par register name gp1par address 0xfffff43c default value 0x22000022 access read/write function gp1par programs the parameters for port 0, port 1, and port 2. note that the gp1dat mmr must always be written after changing the gp1par mmr.
aduc7023 rev. b | page 51 of 96 gp2par register name gp2par address 0xfffff44c default value 0x00000000 access read/write function gp2par programs the parameters for port 0, port 1, and port 2. note that the gp2dat mmr must always be written after changing the gp2par mmr. table 56. gpxpar mmr bit descriptions bit description 31 reserved. 30 to 29 drive strength px.7 28 pull-up disable px.7. 27 reserved. 26 to 26 drive strength px.6 24 pull-up disable px.6. 23 reserved. 22 to 21 drive strength px.5 20 pull-up disable px.5. 19 reserved. 18 to 17 drive strength px.4 16 pull-up disable px.4. 15 reserved. 14 to 13 drive strength px.3 12 pull-up disable px.3. 11 reserved. 10 to 9 drive strength px.2 8 pull-up disable px.2. 7 reserved. 6 to 5 drive strength px.1 4 pull-up disable px.1. 3 reserved. 2 to 1 drive strength px.0 0 pull-up disable px.0. table 57. gpio drive strength control bits descriptions control bits value description 00 medium drive strength. 01 low drive strength. 1x high drive strength. 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 ?24 ?18 ?12 ?6 0 6 12 18 24 load current (ma) voltage on each pin (v) 08675-031 high drive strength medium drive strength low drive strength figure 37. programmable strength for high level 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?24 ?18 ?12 ?6 0 6 12 18 24 load current (ma) voltage on each pin (v) 08675-032 high drive strength medium drive strength low drive strength figure 38. programmable strength for low level the drive strength bits can be written one time only after reset. more writing to related bits has no effect on changing drive strength. the gpio drive strength and pull-up disable is not always adjustable for the gpio port. some control bits cannot be changed (see table 58 ). table 58. gpxpar control bits access descriptions 1 bit gp0par gp1par gp2par 31 reserved reserved reserved 30 to 29 r/w r/w reserved 28 r/w r/w reserved 27 reserved reserved reserved 26 to 26 r/w r/w reserved 24 r/w r/w reserved 23 reserved reserved reserved 22 to 21 r/w r(b00) reserved 20 r/w r/w reserved 19 reserved reserved reserved 18 to 17 r(b00) r(b00) r(b00) 16 r/w r/w r/w 15 reserved reserved reserved 14 to 13 r(b00) r(b00) r(b00) 12 r/w r/w r/w 11 reserved reserved reserved
aduc7023 rev. b | page 52 of 96 bit gp0par gp1par gp2par 10 to 9 r(b00) r(b00) r(b00) 8 r/w r/w r/w 7 reserved reserved reserved 6 to 5 r(b00) r(b00) reserved 4 r/w r/w reserved 3 reserved reserved reserved 2 to 1 r(b00) r(b00) r(b00) 0 r/w r/w r(b0) 1 when p2.0 is configured as ain12, the internal pull-up resistor cannot be disabled. gp0dat register name address default value access gp0dat 0xfffff420 0x000000xx r/w gp1dat 0xfffff430 0x000000xx r/w gp2dat 0xfffff440 0x000000xx r/w gpxdat are port x configuration and data registers. they configure the direction of the gpio pins of port x, set the output value for the pins configured as output, and store the input value of the pins configured as input. table 59. gpxdat mmr bit descriptions bit description 31 to 24 direction of the data. this bit is set to 1 by the user to configure the gpio pin as an output. this bit is cleared to 0 by the user to configure the gpio pin as an input. 23 to 16 port x data output. 15 to 8 reflect the state of port x pins at reset (read only). 7 to 0 port x data input (read only). gp0set register name gp0set address 0xfffff424 default value 0x000000xx access write function gp0set is a data set port x register gp1set register name gp1set address 0xfffff434 default value 0x000000xx access write function gp1set is a data set port x register gp2set register name gp2set address 0xfffff444 default value 0x000000xx access write function gp2set is a data set port x register table 60. gpxset mmr bit descriptions bit description 31 to 24 reserved. 23 to 16 data port x. this bit is set to 1 by the user to set bit on port x; this bit also sets the corresponding bit in the gpxdat mmr. this bit is cleared to 0 by the user; this bit does not affect the data out. 15 to 0 reserved. gp0clr registers name gp0clr address 0xfffff42 default value 0x000000xx access write function gp0clr is a data clear port x register gp1clr registers name gp1clr address 0xfffff43 default value 0x000000xx access write function gp1clr is a data clear port x register gp2clr registers name gp2clr address 0xfffff44 default value 0x000000xx access write function gp2clr is a data clear port x register
aduc7023 rev. b | page 53 of 96 table 61. gpxclr mmr bit descriptions the maximum speed of the spi clock is independent on the clock divider bits. bit description 31 to 24 reserved. in slave mode, the spicon register must be configured with the phase and polarity of the expected input clock. the slave accepts data from an external master up to 10 mbps. 23 to 16 data port x clear bit. this bit is set to 1 by the user to clear the bit on port x; this bit also clears the corresponding bit in the gpxdat mmr. in both master and slave modes, data is transmitted on one edge of the spiclk signal and sampled on the other. therefore, it is important that the polarity and phase are configured the same for the master and slave devices. this bit is cleared to 0 by the user; this bit does not affect the data out. 15 to 0 reserved. spi chip select ( ss input) pin serial peripheral interface in spi slave mode, a transfer is initiated by the assertion of ss , which is an active low input signal. the spi port then transmits and receives 8-bit data until the transfer is concluded by deassertion of ss . in slave mode, ss is always an input. the aduc7023 integrates a complete hardware serial peripheral interface (spi) on chip. spi is an industry standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex up to a maximum bit rate of 20 mbps. in spi master mode, the ss is an active low output signal. it asserts itself automatically at the beginning of a transfer and deasserts itself upon completion. the spi port can be configured for master or slave operation and typically consists of four pins: miso, mosi, spiclk, and spi ss . configuring external pins for spi functionality miso (master in, slave out) pin p1.1 is the slave chip select pin. in slave mode, this pin is an input and must be driven low by the master. in master mode, this pin is an output and goes low at the beginning of a transfer and high at the end of a transfer. the miso pin is configured as an input line in master mode and an output line in slave mode. the miso line on the master (data in) should be connected to the miso line in the slave device (data out). the data is transferred as byte wide (8-bit) serial data, msb first. p1.0 is the sclk pin. mosi (master out, slave in) pin p0.6 is the master in, slave out (miso) pin. the mosi pin is configured as an output line in master mode and an input line in slave mode. the mosi line on the master (data out) should be connected to the mosi line in the slave device (data in). the data is transferred as byte wide (8-bit) serial data, msb first. p0.7 is the master out, slave in (mosi) pin. to configure these pins for spi mode, see the general-purpose input/output section. spi registers the following mmr registers control the spi interface: spista, spirx, spitx, spidiv, and spicon. spi status register spiclk (serial clock i/o) pin the master serial clock (spiclk) synchronizes the data being transmitted and received through the mosi spiclk period. therefore, a byte is transmitted/received after eight spiclk periods. the spiclk pin is configured as an output in master mode and as an input in slave mode. name: spista address: 0xffff0a00 in master mode, polarity and phase of the clock are controlled by the spicon register, and the bit rate is defined in the spidiv register as follows: default value: 0x0000 access: read )1(2 spidiv f f uclk clock serial + = function: this 32-bit mmr contains the status of the spi interface in both master and slave modes. where: f uclk is the clock selected by powcon1 bit 7 to bit 6.
aduc7023 rev. b | page 54 of 96 table 62. spista mmr bit designations bit name description 15 to 12 reserved bits. 11 spirex spi rx fifo excess bytes present. this bit is set when there are more bytes in the rx fifo than indicated in the spimde bits in spicon this bit is cleared when the number of bytes in the fifo is equal or less than the number in spimde. 10 to 8 spirxfsta[2:0] spi rx fifo status bits. [000] = rx fifo is empty. [001] = 1 valid byte in the fifo. [010] = 2 valid byte in the fifo. [011] = 3 valid byte in the fifo. [100] = 4 valid byte in the fifo. 7 spifof spi rx fifo overflow status bit. this bit is set when the rx fifo is full when new data is loaded to the fifo. this bit generates an interrupt except when spirflh is set in spicon. this bit is cleared when the spista register is read. 6 spirxirq spi rx irq status bit. this bit is set when a receive interrupt occurs. this bit is set when spitmde in spicon is cleared and the required number of bytes have been received. this bit is cleared when the spista register is read. 5 spitxirq spi tx irq status bit. this bit is set when a transmit interrupt occurs. this bi t is set when spitmde in spicon is set and the required number of bytes have been transmitted. this bit is cleared when the spista register is read. 4 spitxuf spi tx fifo underflow. this bit is set when a transmit is initiated without any va lid data in the tx fifo. this bit generates an interrupt except when spitflh is set in spicon. this bit is cleared when the spista register is read. 3 to 1 spitxfsta[2:0] spi tx fifo status bits. [000] = tx fifo is empty. [001] = 1 valid byte in the fifo. [010] = 2 valid byte in the fifo. [011] = 3 valid byte in the fifo. [100] = 4 valid byte in the fifo. 0 spiista spi interrupt status bit. this bit is set to 1 when an spi based interrupt occurs. this bit is cleared after reading spista. spirx register name spirx address 0xffff0a04 default value 0x00 access read function this -bit mmr is the spi receive register spitx register name spitx address 0xffff0a0 default value 0xxx access write function this -bit mmr is the spi transmit register
aduc7023 rev. b | page 55 of 96 spidiv register name: spidiv address: 0xffff0a0c default value: 0x00 access: read/write function: this 8-bit mmr is the spi baud rate selection register. spi control register name: spicon address: 0xffff0a10 default value: 0x0000 access: read/write function: this 16-bit mmr configures the spi peripheral in both master and slave modes.
aduc7023 rev. b | page 56 of 96 table 63. spicon mmr bit designations bit name description 15 to 14 spimde spi irq mode bits. these bits config ure when the tx/rx interrupts occur in a transfer. [00] = tx interrupt occurs when one byte has been transferred. rx interrupt occurs when one or more bytes have been received into the fifo. [01] = tx interrupt occurs when two bytes has been transferred. rx interrupt occurs when two or more bytes have been received into the fifo. [10] = tx interrupt occurs when three bytes has been transf erred. rx interrupt occurs when three or more bytes have been received into the fifo. [11] = tx interrupt occurs when four bytes has been transfer red. rx interrupt occurs when the rx fifo is full or four bytes present. 13 spitflh spi tx fifo flush enable bit. this bit is set to flush the tx fifo. this bit does not clear itself and should be toggled if a single flush is required. if this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the spizen bit. any writes to the tx fifo ar e ignored while this bit is set. this bit is cleared to disable tx fifo flushing. 12 spirflh spi rx fifo flush enable bit. this bit is set to flush the rx fifo. this bit does not clear itself and should be toggled if a single flush is required. if this bit is set, all incoming data is ignored and no interrupts are generated. if set and spitmde = 0, a read of the rx fifo initiates a transfer. this bit is cleared to disable rx fifo flushing. 11 spicont continuous transfer enable. this bit is set by the user to enable continuous transfer. in master mode, the transfer cont inues until no valid data is available in the tx register. ss is asserted and remains asserted for the duration of each 8-bit serial transfer until tx is empty. this bit is cleared by the user to disabl e continuous transfer. each transfer cons ists of a single 8-bit serial transfer. if valid data exists in the spitx register, then a new transfer is initiated after a stall period of 1 serial clock cycle. 10 spilp loop back enable bit. this bit is set by the user to conn ect miso to mosi and test software. this bit is cleared by the user to be in normal mode. 9 spioen slave miso output enable bit. this bit is set for miso to operate as normal. this bit is cleared to disable the o utput driver on the miso pin. the miso pi n is open-drain when this bit is clear. 8 spirow spirx overflow overwrite enable. this bit is set by the user; the va lid data in the rx register is overwritten by the new serial byte received. this bit is cleared by the user; the new serial byte received is discarded. 7 spizen spi transmit zeros when tx fifo is empty. this bit is set to transmit 0x00 when there is no valid data in the tx fifo. this bit is cleared to transmit the last transmitte d value when there is no valid data in the tx fifo. 6 spitmde spi transfer and interrupt mode. this bit is set by the user to initiate transfer with a writ e to the spitx register. interrupt only occurs when tx is empty. this bit is cleared by the user to initiate transfer with a read of the spirx register. interrupt only occurs when rx is full . 5 spilf lsb first transfer enable bit. this bit is set by the user ; the lsb is transmitted first. this bit is cleared by the us er; the msb is transmitted first. 4 spiwom spi wired or mode enable bit. this bit is set to 1 enable op en-drain data output. external pull-ups are required on data out pins. this bit is cleared for normal output levels. 3 spicpo serial clock polarity mode bit. this bit is set by the user; the serial clock idles high. this bit is cleared by the user ; the serial clock idles low. 2 spicph serial clock phase mode bit. this bit is set by the user; the serial clock pu lses at the beginning of each serial bit transfer. this bit is cleared by the user; the serial cloc k pulses at the end of each serial bit transfer.
aduc7023 rev. b | page 57 of 96 bit name description 1 spimen master mode enable bit. this bit is set by the us er to enable master mode. this bit is cleared by the user to enable slave mode. 0 spien spi enable bit. this bit is set by the user to enable the spi. this bit is cleared by the user to disable the spi.
aduc7023 rev. b | page 58 of 96 i 2 c serial clock generation the aduc7023 incorporates two i 2 c peripherals that may be configured as a fully i 2 c-compatible i 2 c bus master device or as a fully i 2 c bus-compatible slave device. the i 2 c master in the system generates the serial clock for a transfer. the master channel can be configured to operate in fast mode (400 khz) or standard mode (100 khz). the two pins used for data transfer, sda and scl, are configured in a wire-and format that allows arbitration in a multimaster system. these pins require external pull-up resistors. typical pull-up values are between 4.7 k and 10 k. the bit rate is defined in the i2cdiv mmr as follows: ) (2 )2( divl divh +++ = the i 2 c bus peripheral address in the i 2 c bus system is pro- grammed by the user. this id can be modified any time a transfer is not in progress. the user can configure the interface to respond to four slave addresses. where: f uclk is the clock before the clock divider and the clock selected by powcon1 bit 4 to bit 0. divh is the high period of the clock. divl is the low period of the clock. the transfer sequence of an i 2 c system consists of a master device initiating a transfer by generating a start condition while the bus is idle. the master transmits the slave device address and the direction of the data transfer (read or/write) during the initial address transfer. if the master does not lose arbitration and the slave acknowledges the data, transfer is initiated. this continues until the master issues a stop condition and the bus becomes idle. thus, for 100 khz operation, divh = divl = 0xcf and for 400 khz, divh = 0x28, divl = 0x3c the i2cdiv register corresponds to divh:divl. the i 2 c peripheral can only be configured as a master or slave at any given time. the same i 2 c channel cannot simultaneously support master and slave modes. i 2 c bus addresses slave mode in slave mode, the registers i2cxid0, i2cxid1, i2cxid2, and i2cxid3 contain the device ids. the device compares the four i2cxidx registers to the address byte received from the bus master. to be correctly addressed, the 7 msbs of either id register must be identical to that of the 7 msbs of the first received address byte. the lsb of the id registers (the transfer direction bit) is ignored in the process of address recognition. the i 2 c interface on the aduc7023 includes support for repeated start conditions. in master mode, the aduc7023 can be programmed to generate a repeated start. in slave mode, the aduc7023 recognizes repeated start conditions. in master and slave mode, the part recognizes both 7-bit and 10-bit bus addresses. in i 2 c master mode, the aduc7023 supports continuous reads from a single slave up to 512 bytes in a single transfer sequence. clock stretching is supported in both master and slave modes. in slave mode, the aduc7023 can be programmed to return a nack. this allows the validiation of checksum bytes at the end of i2c transfers. bus arbitration in master mode is supported. internal and external loopback modes are supported for i 2 c hardware testing. in loopback mode. the transmit and receive circuits in both master and slave mode contain 2-byte fifos. status bits are available to the user to control these fifos. the aduc7023 also supports 10-bit addressing mode. when bit 1 of i2cxscon (adr10en bit) is set to 1, then one 10-bit address is supported in slave mode and is stored in registers i2cxid0 and i2cxid1. the 10-bit address is derived as follows: i2cxid0[0] is the read/write bit and is not part of the i 2 c address. i2cxid0[7:1] = address bits[6:0]. i2cxid1[2:0] = address bits[9:7]. configuring external pins for i 2 c functionality i2cxid1[7:3] must be set to 11110b. master mode the i 2 c pins of the aduc7023 device are p0.4 and p0.5 for i 2 c0 and p0.6 and p0.7 for i 2 c1. in master mode, the i2cxadr0 register is programmed with the i 2 c address of the device. p0.4 and p0.6 are the i 2 c clock signals and p0.5 and p0.7 are the i 2 c data signals. for instance, to configure i 2 c0 pins (scl0, sda0), bit 16 and bit 20 of the gp0con register must be set to 1 to enable i 2 c mode. on the other hand, to configure i 2 c1 pins (scl1, sda1), bit 25 and bit 29 of the gp0con register must be set to 1 to enable i 2 c mode, as shown in the gpio section. i 2 c1 function is avaliable at p0.6 and p0.7 on 32-lead package and avaliable at p1.6 and p1.7 on 40-lead pacakge. in 7-bit address mode, i2cxadr0[7:1] are set to the device address. i2cxadr0[0] is the read/write bit. in 10-bit address mode, the 10-bit address is created as follows: i2cxadr0[7:3] must be set to 11110b. i2cxadr0[2:1] = address bits[9:8]. i2cxadr1[7:0] = address bits[7:0]. i2cxadr0[0] is the read/write bit.
aduc7023 revpri| page 59 of 96 i 2 c registers the i 2 c peripheral interfaces consists of a number of mmrs. these are described in the following section. i 2 c master registers i 2 c master control registers, i2cxmcon name: i2c0mcon, i2c1mcon address: 0xffff0800, 0xffff0900 default value: 0x0000, 0x0000 access: read/write function: these 16-bit mmrs configure the i 2 c peripheral in master mode. table 64. i2cxmcon mmr bit designations bit name description 15 to 9 reserved. these bits are reserved and should not be written to. 8 i2cmceni i 2 c transmission complete interrupt enable bit. this bit is set to enable an interrupt on detecting a stop condition on the i 2 c bus. this bit clears th is interrupt source. 7 i2cnackeni i 2 c no acknowledge received interrupt enable bit. this bit is set to enab le interrupts when the i 2 c master receives a no acknowledge. this bit clears th is interrupt source. 6 i2caleni i 2 c arbitration lost interrupt enable bit. this bit is set to enab le interrupts when the i 2 c master has lost in trying to gain control of the i 2 c bus. this bit clears th is interrupt source. 5 i2cmteni i 2 c transmit interrupt enable bit. this bit is set to enab le interrupts when the i 2 c master has transmitted a byte. this bit clears th is interrupt source. 4 i2cmreni i 2 c receive interrupt enable bit. this bit is set to enab le interrupts when the i 2 c master receives data. this bit is cleared by the user to disable interrupts when the i 2 c master is receiving data. 3 i2cmsen i 2 c master scl stretch enable bit. this bit is set to 1 to enable clock stretching. when scl is low, setting this bit forces the device to hold scl low until i2cmsen is cleared. if scl is high, setting this bit fo rces the device to hold scl low after the next falling edge. this bit is cleared to disable clock stretching. 2 i2cilen i 2 c internal loopback enable bit. this bit is set to enable loopback test mode. in this mode, the scl and sda signals are connected internally to their respective input signals. this bit is cleared by the user to disable loopback mode. 1 i2cbd i 2 c master backoff disable bit. this bit is set to allow the device to compete for control of the bus even if another device is currently driving a start condition. this bit is cleared to back off until the i 2 c bus becomes free. 0 i2cmen i 2 c master enable bit. this bit is set by the user to enable i 2 c master mode. this bit is cleared to disable i 2 c master mode.
aduc7023 rev. b | page 60 of 96 i 2 c master status registers, i2cxmsta name: i2c0msta , i2c1msta address: 0xffff0804, 0xffff0904 default value: 0x0000, 0x0000 access: read function: these 16-bit mmrs are the i 2 c status registers in master mode. table 65. i2cxmsta mmr bit designations bit name description 15 to 11 reserved. these bits are reserved. 10 i2cbbusy i 2 c bus busy status bit. this bit is set to 1 when a start condition is detected on the i 2 c bus. this bit is cleared when a stop condition is detected on the bus. 9 i2cmrxfo master rx fifo overflow. this bit is set to 1 when a byte is writte n to the rx fifo when it is already full. this bit is cleared in all other conditions. 8 i2cmtc i 2 c transmission complete status bit. this bit is set to 1 when a transmission is complete between the master and the slave with which it was communicating. if the i2cmceni bit in i2cxmcon is set, an interrupt is generate d when this bit is set. this bit clears th is interrupt source. 7 i2cmna i 2 c master no acknowledge data bit. this bit is set to 1 when a no acknowledge condition is received by the master in response to a data write transfer. if the i2cnackeni bit in i2cxmcon is set, an interrupt is generate d when this bit is set. this bit is cleared in all other conditions. 6 i2cmbusy i 2 c master busy status bit. this bit is set to 1 when the master is busy processing a transaction. this bit is cleared if the master is ready or if another master device has control of the bus. 5 i2cal i 2 c arbitration lost status bit. this bit is set to 1 when the i 2 c master has lost in trying to gain control of the i 2 c bus. if the i2caleni bit in i2c1mcon is set, an interrupt is generated when this bit is set. this bit is cleared in all other conditions. 4 i2cmna i 2 c master no acknowledge address bit. this bit is set to 1 when a no acknowledge condition is received by the master in response to an address. if the i2cnackeni bit in i2c1mcon is set, an in terrupt is generated when this bit is set. this bit is cleared in all other conditions. 3 i2cmrxq i 2 c master receive request bit. this bit is set to 1 when data enters the rx fifo. if the i2cmreni in i2c1mcon is set, an interrupt is generated. this bit is cleared in all other conditions. 2 i2cmtxq i 2 c master transmit request bit. this bit becomes high if the tx fifo is empty or only contains one byte and the master has transmitted an address and write. if the i2cmteni bit in i2c1mcon is set, an interrupt is generated when this bit is set. this bit is cleared in all other conditions. 1 to 0 i2cmtfsta i 2 c master tx fifo status bits. 00 = i 2 c master tx fifo empty. 01 = 1 byte in master tx fifo. 10 = 1 byte in master tx fifo. 11 = i 2 c master tx fifo full.
aduc7023 rev. b | page 61 of 96 i 2 c master receive registers, i2cxmrx name: i2c0mrx, i2c1mrx address: 0xffff0808, 0xffff0908 default value: 0x00 access: read only function: these 8-bit mmrs are the i 2 c master receive registers. i 2 c master transmit registers, i2cxmtx name: i2c0mtx, i2c1mtx address: 0xffff080c 0xffff090c default value: 0x00, 0x00 access: write only function: these 8-bit mmrs are the i 2 c master transmit registers i 2 c master read count registers, i2cxmcnt0 name: i2c0mcnt0, i2c1mcnt0 address: 0xffff0810, 0xffff0910 default value: 0x0000, 0x0000 access: read/write function: these 16-bit mmrs hold the required number of bytes when the master begins a read sequence from a slave device. table 66. i2cxmcnt0 mmr bit descriptions: address = 0xffff0810, 0xffff0910. default value = 0x0000 bit name description 15 to 9 reserved. 8 i2crecnt this bit is set if greater than 256 bytes are required from the slave. this bit is cleared when reading 256 bytes or less. 7 to 0 i2crcnt these eight bits hold the number of bytes required during a slave read sequence, minus 1. if only a single byte is required, these bits should be set to 0. i 2 c master current read count registers, i2cxmcnt1 name: i2c0mcnt1, i2c1mcnt1 address: 0xffff0814, 0xffff0914 default value: 0x00, 0x00 access: read function: these 8-bit mmrs hold the number of bytes received thus far during a read sequence with a slave device. i 2 c address 0 registers, i2cxadr0 name: i2c0adr0, i2c1adr0 address: 0xffff0818, 0xffff0918 default value: 0x00 access: read/write function: these 8-bit mmrs hold the 7-bit slave address and the read/write bit when the master begins communicating with a slave. table 67. i2cxadr0 mmr in 7-bit address mode: address = 0xffff0818, 0xffff0918. default value = 0x00 bit name description 7 to 1 i2cadr these bits contain the 7-bit address of the required slave device. 0 r/w bit 0 is the read/write bit. when this bit = 1, a read sequence is requested. when this bit = 0, a write sequence is requested. table 68. i2cxadr0 mmr in 10-bit address mode bit name description 7 to 3 these bits must be set to [11110b] in 10-bit address mode. 2 to 1 i2cmadr these bits contain addr[9:8] in 10-bit address mode. 0 r/w read/write bit. when this bit = 1, a read sequence is requested. when this bit = 0, a write sequence is requested.
aduc7023 rev. b | page 62 of 96 i 2 c address 1 registers, i2cxadr1 name: i2c0adr1, i2c1adr1 address: 0xffff081c , 0xffff091c default value: 0x00 access: read/write function: these 8-bit mmrs are used in 10-bit addressing mode only. these registers contain the least significant byte of the address. table 69. i2cxadr1 mmr in 10-bit address mode bit name description 7 to 0 i2cladr these bits contain addr[7:0] in 10-bit address mode. i 2 c master clock control register, i2cxdiv name: i2c0div, i2c1div address: 0xffff0824, 0xffff0924 default value: 0x1f1f access: read/write function: these mmrs control the frequency of the i 2 c clock generated by the master on to the scl pin. for further details, see the i 2 c initial section. table 70. i2cxdiv mmr bit name description 15 to 8 divh these bits control the duration of the high period of scl. 7 to 0 divl these bits control the duration of the low period of scl. i 2 c slave registers i 2 c slave control registers, i2cxscon name: i2c0scon, i2c1scon address: 0xffff0828, 0xffff0928 default value: 0x0000 access: read/write function: these 16-bit mmrs configure the i 2 c peripheral in slave mode. table 71. i2cxscon mmr bit designations bit name description 15 to 11 reserved bits. 10 i2cstxeni slave transmit interrupt enable bit. this bit is set to enable an interrupt after a slave transmits a byte. this bit clears th is interrupt source. 9 i2csrxeni slave receive interrupt enable bit. this bit is set to enable an interrupt after the slave receives data. this bit clears th is interrupt source. 8 i2csseni i 2 c stop condition detected interrupt enable bit this bit is set to enable an interrupt on detecting a stop condition on the i 2 c bus. this bit clears th is interrupt source. 7 i2cnacken i 2 c no acknowledge enable bit. this bit is set to no acknowledge the next byte in the transmission sequence. this bit is cleared to let the hardware control the acknowledge/no acknowledge sequence. 6 i2cssen i 2 c slave scl stretch enable bit. this bit is set to 1 to enable clock stretching. when scl is low, setting this bit forces the device to hold scl low until i2cssen is cleared. if scl is high, setting this bit forces the device to hold scl low after the next falling edge. this bit is cleared to disable clock stretching.
aduc7023 rev. b | page 63 of 96 bit name description 5 i2cseten i 2 c early transmit inte rrupt enable bit. this bit is set to enable a transmit request interrupt just after the positive edge of scl during the read bit transmission. this bit is cleared to enable a trans mit request interrupt just after the negative edge of scl during the read bit transmission. 4 i2cgcclr i 2 c general call status and id clear bit. writing a 1 to this bit clears the general ca ll status and id bits in the i2cxssta register. this bit is cleared at all other times. 3 i2chgcen i 2 c hardware general call enable. hardware general call enable. when this bit and bit 2 are set, and having received a general call (address 0x00) and a data byte, th e device checks the contents of the i2cxalt against the receive register. if the contents match, the device ha s received a hardware general call. this is used if a device needs urgent attention from a master device with out knowing which master it needs to turn to. this is a broadcast message to all master devices on the bus. the aduc7023 watches for these addresses. the device that requires attention embeds its own address into the message. all masters listen, and the one that can handle the device contacts its slave and acts appropriately. the lsb of the i2cxalt register should always be written to 1, as per the i 2 c january 2000 bus specification. this bit and i2cgcen are set to enable hardware general call recognition in slave mode. this bit is cleared to disable recognition of hardware general call commands. 2 i2cgcen i 2 c general call enable. this bit is set to enable the slave device to acknowledge an i 2 c general call, address 0x00 (write). the device then recognizes a data bit. if it receives a 0x06 (reset and write programmable part of the slave address by hardware) as the data byte, the i 2 c interface resets as per the i 2 c january 2000 bus specification. this command can be used to reset an entire i 2 c system. if it receives a 0x04 (write programmable part of the slave address by hardware) as th e data byte, the general call interrupt status bit sets on any general call. the user must take correcti ve action by reprogramming the device address. this bit is set to allow the slave acknowledge i 2 c general call commands. this bit is cleared to disable recognition of general call commands. 1 adr10en i 2 c 10-bit address mode. this bit is set to 1 to enable 10-bit address mode. this bit is cleared to 0 to enable normal address mode. 0 i2csen i 2 c slave enable bit. this bit is set by user to enable i 2 c slave mode. this bit is cleared by the user to disable i 2 c slave mode. i 2 c slave status registers, i2cxssta name: i2c0ssta, i2c1ssta address: 0xffff082c, 0xffff092c default value: 0x0000, 0x0000 access: read/write function: these 16-bit mmrs are the i 2 c status registers in slave mode.
aduc7023 rev. b | page 64 of 96 table 72. i2cxssta mmr bit designations bit name description 15 reserved bit. 14 i2csta this bit is set to 1 if: a start condition followed by a matching address is detected. it is also set if a start byte (0x01) is received. if general calls are enabled and a general call code of (0x00) is received. this bit is cleared on receiving a stop condition. 13 i2creps this bit is set to 1 if a repeated start condition is detected. this bit is cleared on receiving a stop condition. 12 to 11 i2cid[1:0] i 2 c address matching register. these bits indicate which i2cxidx register matches the received address. [00] = received address matches i2cxid0. [01] = received address matches i2cxid1. [10] = received address matches i2cxid2. [11] = received address matches i2cxid3. 10 i2css i 2 c stop condition after start detected bit. this bit is set to 1 when a stop condition is de tected after a previous start and matching address. when the i2csseni bit in i2cxscon is set, an interrupt is generated. this bit is cleared by reading this register. 9 to 8 i2cgcid[1:0] i 2 c general call id bits. [00] = no general call received. [01] = general call reset and program address. [10] = general program address. [11] = general call matching alternative id. these bits are not cleared by a general call reset command. these bits are cleared by writing a 1 to the i2cgcclr bit in i2cxscon. 7 i2cgc i 2 c general call status bit. this bit is set to 1 if the slave receives a general call command of any type. if the command received is a reset command, then all registers return to their defa ult state. if the command received is a hardware general call, the rx fifo holds the second byte of the command, and this can be compared with the i2cxalt register. this bit is cleared by writing a 1 to the i2cgcclr bit in i2cxscon. 6 i2csbusy i 2 c slave busy status bit. this bit is set to 1 when the slave receives a start condition. this bit is cleared by hardware if the received addr ess does not match any of the i2cxidx registers, the slave device receives a stop condition or if a repeat ed start address does not match any of the i2cxidx registers. 5 i2csna i 2 c slave no acknowledge data bit. this bit is set to 1 when the slave responds to a bus address with a no acknowledge. this bit is asserted under the following conditions: if no acknowledge is retur ned because there is no data in the tx fifo or if the i2cnacken bit is set in the i2cxscon register. this bit is cleared in all other conditions. 4 i2csrxfo slave rx fifo overflow. this bit is set to 1 when a byte is writte n to the rx fifo when it is already full. this bit is cleared in all other conditions. 3 i2csrxq i 2 c slave receive request bit. this bit is set to 1 when the slave rx fifo is not empty. this bit ca uses an interrupt to occur if the i2csrxeni bit in i2cxscon is set. the rx fifo must be read or flushed to clear this bit. 2 i2cstxq i 2 c slave transmit request bit. this bit is set to 1 when the slave receives a matchi ng address followed by a read. if the i2cseten bit in i2cxscon is = 0, , this bit goes high just after the ne gative edge of scl during the read bit transmission. if the i2cseten bit in i2cxscon is = 1, this bit goes hi gh just after the positive edge of scl during the read bit transmission. this bit causes an interrupt to occur if the i2cstxeni bit in i2cxscon is set. this bit is cleared in all other conditions.
aduc7023 rev. b | page 65 of 96 bit name description 1 i2cstfe i 2 c slave fifo underflow status bit. this bit goes high if the tx fifo is empty when a master requests data from the slave. this bit is asserted at the rising edge of scl during the read bit. this bit is cleared in all other conditions. 0 i2cetsta i 2 c slave early transmit fifo status bit. if the i2cseten bit in i2cxscon is = 0, this bit goes high if the slave tx fifo is empty. if the i2cseten bit in i2cxscon is = 1, this bit goes high just after the positive edge of scl during the write bit transmission. this bit asserts once only for a transfer. this bit is cleared after being read. i 2 c slave receive registers, i2cxsrx name: i2c0srx, i2c1srx address: 0xffff0830, 0xffff0930 default value: 0x00 access: read function: these 8-bit mmrs are the i 2 c slave receive register. i 2 c slave transmit registers, i2cxstx name: i2c0stx, i2c1stx address: 0xffff0834, 0xffff0934 default value: 0x00 access: write function: these 8-bit mmrs are the i 2 c slave transmit registers. i 2 c hardware general call recognition registers, i2cxalt name: i2c0alt, i2c1alt address: 0xffff0838, 0xffff0938 default value: 0x00 access: read/write function: these 8-bit mmrs are used with hardware general calls when the i2cxscon bit 3 is set to 1. these registers are used in cases where a master is unable to generate an address for a slave, and instead, the slave must generate the address for the master. i 2 c slave device id registers, i2cxidx name: i2c0idx, i2c1idx addresses: 0xffff093c = i2c1id0 0xffff083c = i2c0id0 0xffff0940 = i2c1id1 0xffff0840 = i2c0id1 0xffff0944 = i2c1id2 0xffff0844 = i2c0id2 0xffff0948 = i2c1id3 0xffff0848 = i2c0id3 default value: 0x00 access: read/write function: these 8-bit mmrs are programmed with i 2 c bus ids of the slave. see the i 2 c bus addresses section for further details. i 2 c common registers i 2 c fifo status registers, i2cxfsta name: i2c0fsta, i2c1fsta address: 0xffff084c, 0xffff094c default value: 0x0000 access: read/write function: these 16-bit mmrs contain the status of the rx/tx fifos in both master and slave modes.
aduc7023 rev. b | page 66 of 96 table 73. i2cxfsta mmr bit designations bit name description 15 to 10 reserved bits. 9 i2cfmtx this bit is set to 1 to flush the master tx fifo. 8 i2cfstx this bit is set to 1 to flush the slave tx fifo. 7 to 6 i2cmrxsta i 2 c master receive fifo status bits. [00] = fifo empty. [01] = byte written to fifo. [10] = 1 byte in fifo. [11] = fifo full. 5 to 4 i2cmtxsta i 2 c master transmit fifo status bits. [00] = fifo empty. [01] = byte written to fifo. [10] = 1 byte in fifo. [11] = fifo full. 3 to 2 i2csrxsta i 2 c slave receive fifo status bits. [00] = fifo empty [01] = byte written to fifo [10] = 1 byte in fifo [11] = fifo full 1 to 0 i2cstxsta i 2 c slave transmit fifo status bits. [00] = fifo empty. [01] = byte written to fifo. [10] = 1 byte in fifo. [11] = fifo full. programmable logic array (pla) every aduc7023 integrates a fully programmable logic array (pla) consisting of sixteen pla elements. each pla element contains a two-input look-up table that can be configured to generate any logic output function based on two inputs and a flip-flop. this is represented in figure 39 . 08675-033 4 2 0 1 3 a b look-up table figure 39. pla element in total, 20 gpio pins are available on the aduc7023 for the pla. these include 11 input pins and nine output pins, which need to be configured in the gpxcon register as pla pins before using the pla. the pla is configured via a set of user mmrs. the output(s) of the pla can be routed to the internal interrupt system, to the conv start signal of the adc, to an mmr, or to any of the eight pla output pins. table 74. element input/output pla block 0 pla block 1 element input output element input output 0 p0.4 p0.7 8 p0.0 p0.2 1 p0.5 p1.0 9 p0.1 p0.3 2 p0.6 p1.1 10 p2.4 p2.5 1 3 p1.2 p1.4 11 nc nc 4 p1.3 p1.5 12 nc nc 5 p1.6 p2.1 1 13 nc nc 6 p1.7 p2.2 14 nc nc 7 p2.0 p2.3 15 nc nc 1 internal pins only. read via gpxdat register.
aduc7023 rev. b | page 67 of 96 pla mmrs interface the pla peripheral interface consists of the 22 mmrs described in the following sections. plaelmx registers plaelmx are element 0 to element 15 control registers. they configure the input and output mux of each element, select the func tion in the look-up table, and bypass/use the flip-flop (see tabl e 76 ). table 75. plaelmx registers name address default value access plaelm0 0xffff0b00 0x0000 r/w plaelm1 0xffff0b04 0x0000 r/w plaelm2 0xffff0b08 0x0000 r/w plaelm3 0xffff0b0c 0x0000 r/w plaelm4 0xffff0b10 0x0000 r/w plaelm5 0xffff0b14 0x0000 r/w plaelm6 0xffff0b18 0x0000 r/w plaelm7 0xffff0b1c 0x0000 r/w plaelm8 0xffff0b20 0x0000 r/w plaelm9 0xffff0b24 0x0000 r/w plaelm10 0xffff0b28 0x0000 r/w plaelm11 0xffff0b2c 0x0000 r/w plaelm12 0xffff0b30 0x0000 r/w plaelm13 0xffff0b34 0x0000 r/w plaelm14 0xffff0b38 0x0000 r/w plaelm15 0xffff0b3c 0x0000 r/w table 76. plaelmx mmr bit descriptions bit value description 31 to 11 reserved. 10 to 9 mux 0 control (see table 80 ). 8 to 7 mux 1 control (see table 80 ). 6 mux 2 control. this bit is set by the user to select the output of mux 0. this bit is cleared by the user to se lect the bit value from the pladin register. 5 mux 3 control. this bit is set by the user to select the input pin of the particular element. this bit is cleared by the user to select the output of mux 1. 4 to 1 look-up table control. 0000 0. 0001 nor. 0010 b and not a. 0011 not a. 0100 a and not b. 0101 not b. 0110 exor. 0111 nand. 1000 and. 1001 exnor. 1010 b. 1011 not a or b. 1100 a. 1101 a or not b. 1110 or. 1111 1.
aduc7023 rev. b | page 68 of 96 bit value description 0 mux 4 control. this bit is set by the user to bypass the flip-flop. this bit is cleared by the user to se lect the flip-flop (cleared by default). placlk register name: placlk address: 0xffff0b40 default value: 0x00 access: read/write function: placlk is the clock selection for the flip- flops. the maximum frequency when using the gpio pins as the clock input for the pla blocks is 41.78 mhz. table 77. placlk mmr bit descriptions bit value description 31 to 7 reserved. 6 to 4 clock source selection. 000 gpio clock on p0.5. 001 gpio clock on p1.1. 010 gpio clock on p1.6. 011 hclk. 100 external 32.768 khz crystal. 101 timer1 overflow. 110 uclk. 111 internal 32,768 oscillator. 3 reserved. 2 to 0 clock source selection. 000 gpio clock on p0.5. 001 gpio clock on p1.1. 010 gpio clock on p1.6. 011 hclk. 100 external 32.768 khz crystal. 101 timer1 overflow. 110 uclk. 111 internal 32,768 oscillator. plairq register name: plairq address: 0xffff0b44 default value: 0x00000000 access: read/write function: plairq enables irq0 and/or irq1 and selects the source of the irq. table 78. plairq mmr bit descriptions bit value description 31 to 13 reserved. 12 pla irq1 enable bit. 11 to 8 0000 pla element 0. 0001 pla element 1. 0010 pla element 2. 0011 pla element 3. 0100 pla element 4. 0101 pla element 5. 0110 pla element 6. 0111 pla element 7. 1000 pla element 8. 1001 pla element 9. 1010 pla element 10. 1011 pla element 11. 1100 pla element 12. 1101 pla element 13. 1110 pla element 14. 1111 pla element 15. 7 to 5 reserved. 4 pla irq0 enable bit. this bit is set by the user to enable irq0 output from pla. this bit is cleared by the user to disable irq0 output from pla. 3 to 0 pla irq0 source. 0000 pla element 0. 0001 pla element 1. 0010 pla element 2. 0011 pla element 3. 0100 pla element 4. 0101 pla element 5. 0110 pla element 6. 0111 pla element 7. 1xxx reserved.
aduc7023 rev. b | page 69 of 96 table 79. feedback configuration bit value plaelm0 plaelm1 to plae lm7 plaelm8 plaelm9 to plaelm15 10 to 9 00 element 15 element 0 element 7 element 8 01 element 2 element 2 element 10 element 10 10 element 4 element 4 element 12 element 12 11 element 6 element 6 element 14 element 14 8 to 7 00 element 1 element 1 element 9 element 9 01 element 3 element 3 element 11 element 11 10 element 5 element 5 element 13 element 13 11 element 7 element 7 element 15 element 15 plaadc register name: plaadc address: 0xffff0b48 default value: 0x00000000 access: read/write function: plaadc is the pla source for the adc start conversion signal. table 80. plaadc mmr bit descriptions bit value description 31 to 5 reserved. 4 adc start conversion enable bit. this bit is set by the user to enable adc start conversion from pla. this bit is cleared by the user to disable adc start conversion from pla. 3 to 0 adc start conversion source. 0000 pla element 0. 0001 pla element 1. 0010 pla element 2. 0011 pla element 3. 0100 pla element 4. 0101 pla element 5. 0110 pla element 6. 0111 pla element 7. 1000 pla element 8. 1001 pla element 9. 1010 pla element 10. 1011 pla element 11. 1100 pla element 12. 1101 pla element 13. 1110 pla element 14. 1111 pla element 15. pladin register name: pladin address: 0xffff0b4c default value: 0x00000000 access: read/write function: pladin is a data input mmr for pla. table 81. pladin mmr bit descriptions bit description 31 to 16 reserved. 15 to 0 input bit to element 15 to element 0. pladout register name: pladout address: 0xffff0b50 default value: 0x00000000 access: read function: pladout is a data output mmr for pla. this register is always updated. table 82. pladout mmr bit descriptions bit description 31 to 16 reserved. 15 to 0 output bit from element 15 to element 0. plalck register name: plalck address: 0xffff0b54 default value: 0x00 access: write function: plalck is a pla lock option. bit 0 is written only once. when set, it does not allow modifying any of the pla mmrs, except pladin. a pla tool is provided in the development system to easily configure the pla.
aduc7023 rev. b | page 70 of 96 pulse-width modulator pulse-width modulator general overview the aduc7023 integrates a 5-channel pulse-width modulator (pwm) interface. the pwm outputs can be configured to drive an h-bridge or can be used as standard pwm outputs. on power-up, the pwm outputs default to h-bridge mode. this ensures that the motor is turned off by default. in standard pwm mode, the outputs are arranged as three pairs of pwm pins. users have control over the period of each pair of outputs and over the duty cycle of each individual output. table 83. pwm mmrs mmr name description pwmcon1 pwm control register 1. pwm0com0 compare register 0 for pwm output 0 and pwm output 1. pwm0com1 compare register 1 for pwm output 0 and pwm output 1. pwm0com2 compare register 2 for pwm output 0 and pwm output 1. pwm0len frequency control for pwm output 0 and pwm output 1. pwm1com0 compare register 0 for pwm output 2 and pwm output 3. pwm1com1 compare register 1 for pwm output 2 and pwm output 3. pwm1com2 compare register 2 for pwm output 2 and pwm output 3. pwm1len frequency control for pwm output 2 and pwm output 3. pwm2com0 compare register 0 for pwm output 4 pwm2com1 compare register 1 for pwm output 4 pwmclri pwm interrupt clear. in all modes, the pwmxcomx mmrs control the point at which the pwm outputs change state. an example of the first pair of pwm outputs (pwm0 and pwm1) is shown in figure 40 . high side (pwm0) low side (pwm1) pwm0com2 pwm0com1 pwm0com0 pwm0len 0 7079-020 figure 40. pwm timing the pwm clock is selectable via pwmcon1 with one of the following values: uclk divided by 2, 4, 8, 16, 32, 64, 128, or 256. the length of a pwm period is defined by pwmxlen. the pwm waveforms are set by the count value of the 16-bit timer and the compare registers contents, as shown with the pwm0 and pwm1 waveforms in figure 40 . the low-side waveform, pwm1, goes high when the timer count reaches pwm0len, and it goes low when the timer count reaches the value held in pwm0com2 or when the high-side waveform (pwm0) goes low. the high-side waveform, pwm0, goes high when the timer count reaches the value held in pwm0com0, and it goes low when the timer count reaches the value held in pwm0com1. pwmcon1 control register name: pwmcon1 address: 0xffff0f80 default value: 0x0012 access: read and write function: this is a 16-bit mmr that configures the pwm outputs.
aduc7023 rev. b | page 71 of 96 table 84. pwmcon1 mmr bit designations bit name description 14 sync enables pwm synchronization. set to 1 by the user so that all pwm counters are reset on the next clock edge after the detection of a high-to-low transition on the p2.2/sync pin. cleared by the user to ignore transitions on the p2.2/sync pin. 13 reserved set to 0 by the user. 12 pwm3inv set to 1 by the user to invert pwm3. cleared by the user to use pwm3 in normal mode. 11 pwm1inv set to 1 by the user to invert pwm1. cleared by the user to use pwm1 in normal mode. 10 pwmtrip set to 1 by the user to enable pwm trip inte rrupt. when the pwm trip input (pin p1.5/pwm tripinput ) is low, the pwmen bit is cleared and an interrupt is generated. cleared by the user to disable the pwmtrip interrupt. 9 ena if hoff = 0 and hmode = 1. note that, if not in h-bridge mode, this bit has no effect. set to 1 by the user to enable pwm outputs. cleared by the user to disable pwm outputs. if hoff = 1 and hmode = 1, see table 85 . 8 to 6 pwmcp[2:0] pwm clock prescaler bits. sets the uclk divider. [000] = uclk/2. [001] = uclk/4. [010] = uclk/8. [011] = uclk/16. [100] = uclk/32. [101] = uclk/64. [110] = uclk/128. [111] = uclk/256. 5 poinv set to 1 by the user to invert all pwm outputs. cleared by the user to use pwm outputs as normal. 4 hoff high side off. set to 1 by the user to force pwm0 and pwm2 o utputs high. this also forces pwm1 and pwm3 low. cleared by the user to us e the pwm outputs as normal. 3 lcomp load compare registers. set to 1 by the user to load the internal compare register s with the values in pwmxcomx on the next transition of the pwm timer from 0x00 to 0x01. cleared by the user to use the values previo usly stored in the internal compare registers. 2 dir direction control. set to 1 by the user to enable pwm0 and pwm1 as the output signals while pwm2 and pwm3 are held low. cleared by the user to enable pwm2 and pwm3 as the output signals while pwm0 and pwm1 are held low. 1 hmode enables h-bridge mode. 1 set to 1 by the user to enable h-bridge mode. cleared by the user to operate the pwms in standard mode. 0 pwmen set to 1 by the user to enable all pwm outputs. cleared by the user to disable all pwm outputs. 1 in h-bridge mode, hmode = 1. see table 85 to determine the pwm outputs.
aduc7023 rev. b | page 72 of 96 on power-up, pwmcon1 defaults to 0x0012 (hoff = 1 and hmode = 1). all gpio pins associated with the pwm are configured in pwm mode by default (see table 85 ). clear the pwm trip interrupt by writing any value to the pwmclri mmr. note that when using the pwm trip interrupt, clear the pwm interrupt before exiting the isr. this prevents generation of multiple interrupts. table 85. pwm output selection pwmcon1 mmr 1 pwm outputs 2 ena hoff poinv dir pwm0 pwm1 pwm2 pwm3 0 0 x x 1 1 1 1 x 1 x x 1 0 1 0 1 0 0 0 0 0 hs1 ls1 1 0 0 1 hs1 ls1 0 0 1 0 1 0 hs1 ls1 1 1 1 0 1 1 1 1 hs1 ls1 1 x is dont care. 2 hs = high side, ls = low side. table 86. compare registers name address default value access pwm0com0 0xffff0f84 0x0000 r/w pwm0com1 0xffff0f88 0x0000 r/w pwm0com2 0xffff0f8c 0x0000 r/w pwm1com0 0xffff0f94 0x0000 r/w pwm1com1 0xffff0f98 0x0000 r/w pwm1com2 0xffff0f9c 0x0000 r/w pwm2com0 0xffff0fa4 0x0000 r/w pwm2com1 0xffff0fa8 0x0000 r/w
aduc7023 rev. b | page 73 of 96 pwm0com0 compare register name: pwm0com0 address: 0xffff0f84 default value: 0x0000 access: read and write function: pwm0 output pin goes high when the pwm timer reaches the count value stored in this register. pwm0com1 compare register name: pwm0com1 address: 0xffff0f88 default value: 0x0000 access: read and write function: pwm0 output pin goes low when the pwm timer reaches the count value stored in this register. pwm0com2 compare register name: pwm0com2 address: 0xffff0f8c default value: 0x0000 access: read and write function: pwm1 output pin goes low when the pwm timer reaches the count value stored in this register. pwm0len register name: pwm0len address: 0xffff0f90 default value: 0x0000 access: read and write function: pwm1 output pin goes high when the pwm timer reaches the value stored in this register. pwm1com0 compare register name: pwm1com0 address: 0xffff0f94 default value: 0x0000 access: read and write function: pwm2 output pin goes high when the pwm timer reaches the count value stored in this register. pwm1com1 compare register name: pwm1com1 address: 0xffff0f98 default value: 0x0000 access: read and write function: pwm2 output pin goes low when the pwm timer reaches the count value stored in this register. pwm1com2 compare register name: pwm1com2 address: 0xffff0f9c default value: 0x0000 access: read and write function: pwm3 output pin goes low when the pwm timer reaches the count value stored in this register. pwm1len register name: pwm1len address: 0xffff0fa0 default value: 0x0000 access: read and write function: pwm3 output pin goes high when the pwm timer reaches the value stored in this register.
aduc7023 rev. b | page 74 of 96 pwm2com0 compare register name: pwm2com0 address: 0xffff0fa4 default value: 0x0000 access: read/write function: pwm4 output pin goes high when the pwm timer reaches the count value stored in this register. pwm2com1 compare register name: pwm2com1 address: 0xffff0fa8 default value: 0x0000 access: read/write function: pwm4 output pin goes low when the pwm timer reaches the count value stored in this register. pwmclri register name: pwmclri address: 0xffff0fb8 default value: 0x0000 access: write function: write any value to this register to clear a pwm interrupt source. this register must be written to before exiting a pwm interrupt service routine; otherwise, multiple interrupts occur.
aduc7023 rev. b | page 75 of 96 processor reference peripherals interrupt system there are 22 interrupt sources on the aduc7023 that are controlled by the interrupt controller. most interrupts are generated from the on-chip peripherals, such as adc. four additional interrupt sources are generated from external interrupt request pins, irq0, irq1, irq2, and irq3. the arm7tdmi cpu core only recognizes interrupts as one of two types, a normal interrupt request irq or a fast interrupt request fiq. all the interrupts can be masked separately. the control and configuration of the interrupt system is managed through nine interrupt related registers, four dedicated to irq, and four dedicated to fiq. an additional mmr is used to select the programmed interrupt source. the bits in each irq and fiq registers represent the same interrupt source as described in table 87 . the aduc7023 contains a vectored interrupt controller (vic) that supports nested interrupts up to eight levels. the vic also allows the programmer to assign priority levels to all interrupt sources. interrupt nesting is enabled by setting the enirqn bit in the irqconn register. a number of extra mmrs are used when the full-vectored interrupt controller is enabled. irqsta/fiqsta should be saved immediately upon entering the interrupt service routine (isr) to ensure that all valid interrupt sources are serviced. table 87. irq/fiq mmrs bit description bit description 0 all interrupts ored (fiq only). 1 swi. 2 timer0. 3 timer1. 4 watchdog timer (timer 2). 5 flash control. 6 adc channel. 7 pll lock. 8 i 2 c0 master. 9 i 2 c0 slave. 10 i 2 c1 master. 11 i 2 c1 slave. 12 spi. 13 external irq0. 14 comparator. 15 psm. 16 external irq1. 17 pla irq0. 18 external irq2. 19 external irq3. 20 pla irq1. 21 pwm. irq the interrupt request (irq) is the exception signal to enter the irq mode of the processor. it is used to service general-purpose interrupt handling of internal and external events. the four 32-bit registers dedicated to irq are: irqsta, irqsig, irqen, and irqclr. irqsta register name: irqsta address: 0xffff0000 default value: 0x00000000 access: read function: irqsta (read-only register) provides the current-enabled irq source status. when set to 1, that source generates an active irq request to the arm7tdmi core. there is no priority encoder or interrupt vector generation. this function is implemented in software in a common interrupt handler routine. all 32 bits are logically ored to create the irq signal to the arm7tdmi core. irqsig register name: irqsig address: 0xffff0004 default value: 0x00xxx000 access: read function: irqsig reflects the status of the different irq sources. if a peripheral generates an irq signal, the corresponding bit in the irqsig is set; otherwise, it is cleared. the irqsig bits are cleared when the interrupt in the particular peripheral is cleared. all irq sources can be masked in the irqen mmr. irqsig is read-only.
aduc7023 rev. b | page 76 of 96 irqen register name: irqen address: 0xffff0008 default value: 0x00000000 access: read/write function: irqen provides the value of the current enable mask. when each bit is set to 1, the source request is enabled to create an irq exception. when each bit is set to 0, the source request is disabled or masked, which does not create an irq exception. to clear an already enabled interrupt source, users must set the appropriate bit in the irqclr register. clearing an interrupt irqen bit does not disable this interrupt. irqclr register name: irqclr address: 0xffff000c default value: 0x00000000 access: write function: irqclr (write-only register) clears the irqen register to mask an interrupt source. each bit set to 1 clears the corresponding bit in the irqen register without affecting the remaining bits. the pair of registers, irqen and irqclr, independently manipulate the enable mask without requiring an atomic read-modify-write. fast interrupt request (fiq) the fast interrupt request (fiq) is the exception signal to enter the fiq mode of the processor. it is provided to service data transfer or communication channel tasks with low latency. the fiq interface is identical to the irq interface and provides the second level interrupt (highest priority). four 32-bit registers are dedicated to fiq: fiqsig, fiqen, fiqclr, and fiqsta. bit 31 to bit 1 of fiqsta are logically ored to create the fiq signal to the core and to bit 0 of both the fiq and irq registers (fiq source). the logic for fiqen and fiqclr does not allow an interrupt source to be enabled in both irq and fiq masks. a bit set to 1 in fiqen clears, as a side effect, the same bit in irqen. likewise, a bit set to 1 in irqen clears, as a side effect, the same bit in fiqen. an interrupt source can be disabled in both irqen and fiqen masks. fiqsig fiqsig reflects the status of the different fiq sources. if a peripheral generates an fiq signal the corresponding bit in the fiqsig is set, otherwise it is cleared. the fiqsig bits are cleared when the interrupt in the particular peripheral is cleared. all fiq sources can be masked in the fiqen mmr. fiqsig is read only. fiqsig register name: fiqsig address: 0xffff0104 default value: 0x00000000 access: read only fiqen fiqen provides the value of the current enable mask. when a bit is set to 1, the corresponding source request is enabled to create an fiq exception. when a bit is set to 0, the corre- sponding source request is disabled or masked which does not create an fiq exception. the fiqen register cannot be used to disable an interrupt. fiqen register name: fiqen address: 0xffff0108 default value: 0x00000000 access: read/write fiqclr fiqclr is a write-only register that allows the fiqen register to clear in order to mask an interrupt source. each bit that is set to 1 clears the corresponding bit in the fiqen register without affecting the remaining bits. the pair of registers, fiqen and fiqclr, allows independent manipulation of the enable mask without requiring an atomic read-modify-write. this register should only be used to disable an interrupt source when in the interrupt sources interrupt service routine or if the peripheral is temporarily disabled by its own control register. this register should not be used to disable an irq source if that irq source has an interrupt pending or could have an interrupt pending. fiqclr register name: fiqclr address: 0xffff010c default value: 0x00000000 access: write only
aduc7023 rev. b | page 77 of 96 fiqsta fiqsta is a read-only register that provides the current enabled fiq source status (effectively a logic and of the fiqsig and fiqen bits). when set to 1, that source generates an active fiq request to the arm7tdmi core. there is no priority encoder or interrupt vector generation. this function is implemented in software in a common interrupt handler routine. fiqsta register name: fiqsta address: 0xffff0100 default value: 0x00000000 access: read only programmed interrupts because the programmed interrupts are not maskable, they are controlled by another register (swicfg) that writes into both irqsta and irqsig registers a nd/or the fiqsta and fiqsig registers at the same time. the 32-bit register dedicated to software interrupt is swicfg described in table 88 . this mmr allows the control of a programmed source interrupt. table 88. swicfg mmr bit designations bit description 31 to 3 reserved. 2 programmed interrupt fiq. setting/clearing this bit corresponds to setting/clearing bit 1 of fiqsta and fiqsig. 1 programmed interrupt irq. se tting/clearing this bit corresponds to setting/clearing bit 1 of irqsta and irqsig. 0 reserved. any interrupt signal must be active for at least the minimum interrupt latency time, to be detected by the interrupt controller and to be detected by the user in the irqsta and fiqsta registers. pointer to function (irqvec) irq_source fiq_source programmable priority per interrupt (irqp0/irqp1/irqp2) internal arbiter logic interrupt vector 08675-035 bit 31 to bit 23 unused bit 1 to bit 0 lbss bit 22 to bit 7 (irqbase) bit 6 to bit 2 highest priority active irq figure 41. interrupt structure v ectored interrupt controller (vic) t he aduc7023 incorporates an enhanced interrupt control system or vectored interrupt controller. the vectored interrupt controller for irq interrupt sources is enabled by setting bit 0 of the irqconn register. simila rly, bit 1 of irqconn enables the vectored interrupt controller for the fiq interrupt sources. the vectored interrupt controller provides the following enhancements to the standard irq/fiq interrupts: ? vectored interrupts allow a user to define separate interrupt service routine addresses for every interrupt source. this is achieved by using the irqbase and irqvec registers. ? irq/fiq interrupts can be nested up to eight levels depending on the priority settings. an fiq still has a higher priority than an irq. therefore, if the vic is enabled for both the fiq and irq and prioritization is maximized, then it is possible to have 16 separate interrupt levels. ? programmable interrupt priorities, using the irqp0 to irqp2 registers, can be assigned an interrupt priority level value between 0 and 7. vic mmrs irqbase register the vector base register, irqbase, is used to point to the start address of memory used to store 32 pointer addresses. these pointer addresses are the addresses of the individual interrupt service routines. name: irqbase address: 0xffff0014 default value: 0x00000000 access: read and write table 89. irqbase mmr bit designations bit type initial value description 31:16 read only reserved always read as 0. 15:0 r/w 0 vector base address.
aduc7023 rev. b | page 78 of 96 irqvec register the irq interrupt vector register, irqvec, points to a memory address containing a pointer to the interrupt service routine of the currently active irq. this register should only be read when an irq occurs and irq interrupt nesting has been enabled by setting bit 0 of the irqconn register. irqvec register name: irqvec address: 0xffff001c default value: 0x00000000 access: read only table 90. irqvec mmr bit designations bit type initial value description 31 to 23 read only 0 always read as 0. 22 to 7 r/w 0 irqbase register value. 6 to 2 read only 0 highest priority source. this is a value between 0 and 21 representing the possible interrupt sources. for example, if the highest currently active irq is timer 2, then these bits are [00100]. 1 to 0 reserved 0 reserved bits. priority registers the irq interrupt vector register, irqvec, points to a memory address containing a pointer to the interrupt service routine of the currently active irq. this register should only be read when an irq occurs and irq interrupt nesting has been enabled by setting bit 0 of the irqconn register.
aduc7023 rev. b | page 79 of 96 irqp0 register name: irqp0 address: 0xffff0020 default value: 0x00000000 access: read and write table 91. irqp0 mmr bit designations bit name description 31 reserved reserved bit 30 to 28 pllpi a priority level of 0 to 7 can be set for pll lock interrupt. 27 reserved reserved bit 26 to 24 adcpi a priority level of 0 to 7 can be set for the adc interrupt source. 23 reserved reserved bit 22 to 20 flashpi a priority level of 0 to 7 can be set for the flash controller interrupt source. 19 reserved reserved bit. 18 to 16 t2pi a priority level of 0 to 7 can be set for timer2. 15 reserved reserved bit. 14 to 12 t1pi a priority level of 0 to 7 can be set for timer1. 11 reserved reserved bit. 10 to 8 t0pi a priority level of 0 to 7 can be set for timer0. 7 reserved reserved bit 6 to 4 swintp a priority level of 0 to 7 can be set for the software interrupt source. 3 to 0 reserved interrupt 0 cannot be prioritized. irqp1 register name: irqp1 address: 0xffff0024 default value: 0x00000000 access: read and write table 92. irqp1 mmr bit designations bit name description 31 reserved reserved bit. 30 to 28 psmpi a priority level of 0 to 7 can be set for the power supply monitor interrupt source. 27 reserved reserved bit. 26 to 24 compi a priority level of 0 to 7 can be set for comparator. 23 reserved reserved bit. 22 to 20 irq0pi a priority level of 0 to 7 can be set for irq0. 19 reserved reserved bit. bit name description 18 to 16 spipi a priority level of 0 to 7 can be set for spi. 15 reserved reserved bit. 14 to 12 i2c1spi a priority level of 0 to 7 can be set for i 2 c1 slave. 11 reserved reserved bit. 10 to 8 i2c1mpi a priority level of 0 to 7 can be set for i 2 c1 master. 7 reserved reserved bits. 6 to 4 i2c0spi a priority level of 0 to 7 can be set for i 2 c0 slave. 3 reserved reserved bits. 2 to 0 i2c0mpi a priority level of 0 to 7 can be set for i 2 c0 master. irqp2 register name: irqp2 address: 0xffff0028 default value: 0x00000000 access: read and write table 93. irqp2 mmr bit designations bit name description 31 to 23 reserved reserved bit. 22 to 20 pwmpi a priority level of 0 to 7 can be set for pwm. 19 reserved reserved bit. 18 to 16 pla1pi a priority level of 0 to 7 can be set for pla irq1. 15 reserved reserved bit. 14 to 12 irq3pi a priority level of 0 to 7 can be set for irq3. 11 reserved reserved bit. 10 to 8 irq2pi a priority level of 0 to 7 can be set for irq2. 7 reserved reserved bit. 6 to 4 pla0pi a priority level of 0 to 7 can be set for pla irq0. 3 reserved reserved bit. 2 to 0 irq1pi a priority level of 0 to 7 can be set for irq1.
aduc7023 rev. b | page 80 of 96 irqconn register the irqconn register is the irq and fiq control register. it contains two active bits. the first to enable nesting and prioritization of irq interrupts and the other to enable nesting and prioritization of fiq interrupts. if these bits are cleared, then fiqs and irqs may still be used, but it is not possible to nest irqs or fiqs. neither is it possible to set an interrupt source priority level. in this default state, an fiq does have a higher priority than an irq. name: irqconn address: 0xffff0030 default value: 0x00000000 access: read and write table 94. irqconn mmr bit designations bit name description 31 to 2 reserved these bits are reserved and should not be written to. 1 enfiqn this bit is set to 1 to enable nesting of fiq interrupts. this bit is cleared to mean no nesting or prioritization of fiqs is allowed. 0 enirqn this bit is set to 1 to enable nesting of irq interrupts. when this bit is cleared, it means no nesting or prioritization of irqs is allowed. irqstan register if irqconn bit 0 is asserted and irqvec is read then one of these bits is asserted. the bit that asserts depends on the priority of the irq. if the irq is of priority 0, then bit 0 asserts. if the irq is of priority 1, then bit 1 asserts, and so forth. when a bit is set in this register, all interrupts of that priority and lower are blocked. to clear a bit in this register, all bits of a higher priority must be cleared first. it is only possible to clear one bit at a time. for example, if this register is set to 0x09, then writing 0xff changes the register to 0x08, and writing 0xff a second time changes the register to 0x00. name: irqstan address: 0xffff003c default value: 0x00000000 access: read and write table 95. irqstan mmr bit designations bit name description 31 to 8 reserved these bits are reserved and should not be written to. 7 to 0 this bit is set to 1 to enable nesting of fiq interrupts. when this bit is cleared, it means no nesting or prioritization of fiqs is allowed. fiqvec register the fiq interrupt vector register, fiqvec, points to a memory address containing a pointer to the interrupt service routine of the currently active fiq. this register should only be read when an fiq occurs and fiq interrupt nesting has been enabled by setting bit 1 of the irqconn register. name: fiqvec address: 0xffff011c default value: 0x00000000 access: read only table 96. fiqvec mmr bit designations bit type initial value description 31 to 23 read only 0 always read as 0. 22 to 7 r/w 0 irqbase register value. 6 to 2 0 highest priority source. this is a value between 0 and 27 that represents the possible interrupt sources. for example, if the highest currently active fiq is timer 2, then these bits are [00100]. 1 to 0 reserved 0 reserved bits. fiqstan register if irqconn bit 1 is asserted and fiqvec is read, then one of these bits assert. the bit that asserts depends on the priority of the fiq. if the fiq is of priority 0, then bit 0 asserts. if the fiq is of priority 1, then bit 1 asserts, and so forth. when a bit is set in this register, all interrupts of that priority and lower are blocked.
aduc7023 rev. b | page 81 of 96 to clear a bit in this register, all bits of a higher priority must be cleared first. it is only possible to clear one bit at a time. for example, if this register is set to 0x09, then writing 0xff changes the register to 0x08 and writing 0xff a second time changes the register to 0x00. name: fiqstan address: 0xffff013c default value: 0x00000000 access: read/write table 97. fiqstan mmr bit designations bit name description 31 to 8 reserved these bits are reserved and should not be written to. 7 to 0 this bit is set to 1 to enables nesting of fiq interrupts. when this bit is cleared, it means no nesting or prioritization of fiqs is allowed. external interrupts and pla interrupts the aduc7023 provides up to four external interrupt sources and two pla interrupt sources. these external interrupts can be individually configured as level or rising/falling edge triggered. to enable the external interrupt source or the pla interrupt source, the appropriate bit must be set in the fiqen or irqen register. to select the required edge or level to trigger on, the irqcone register must be appropriately configured. to properly clear an edge-based external irq interrupt or an edge-based pla interrupt, set the appropriate bit in the irqclre register. irqcone register name: irqcone address: 0xffff0034 default value: 0x00000000 access: read and write table 98. irqcone mmr bit designations bit value name description 31 to 12 reserved these bits are reserved and should not be written to. 11 to 10 11 pla1src[1:0] pla irq1 triggers on falling edge. 10 pla irq1 triggers on rising edge. 01 pla irq1 triggers on low level. 00 pla irq1 triggers on high level. bit value name description 9 to 8 11 irq3src[1:0] external irq3 triggers on falling edge. 10 external irq3 triggers on rising edge. 01 external irq3 triggers on low level. 00 external irq3 triggers on high level. 7 to 6 11 irq2src[1:0] external irq2 triggers on falling edge. 10 external irq2 triggers on rising edge. 01 external irq2 triggers on low level. 00 external irq2 triggers on high level. 5 to 4 11 pla0src[1:0] pla irq0 triggers on falling edge. 10 pla irq0 triggers on rising edge. 01 pla irq0 triggers on low level. 00 pla irq0 triggers on high level. 3 to 2 11 irq1src[1:0] external irq1 triggers on falling edge. 10 external irq1 triggers on rising edge. 01 external irq1 triggers on low level. 00 external irq1 triggers on high level. 1 to 0 11 irq0src[1:0] external irq0 triggers on falling edge. 10 external irq0 triggers on rising edge. 01 external irq0 triggers on low level. 00 external irq0 triggers on high level. irqclre register name: irqclre address: 0xffff0038 default value: 0x00000000 access: read and write
aduc7023 rev. b | page 82 of 96 table 99. irqclre mmr bit designations bit name description 31 to 21 reserved these bits are reserved and should not be written to. 20 pla1clri a 1 must be written to this bit in the pla irq1 interrupt service routine to clear an edge triggered pla irq1 interrupt. 19 irq3clri a 1 must be written to this bit in the external irq3 interrupt service routine to clear an edge triggered irq3 interrupt. 18 irq2clri a 1 must be written to this bit in the external irq2 interrupt service routine to clear an edge triggered irq2 interrupt. 17 pla0clri a 1 must be written to this bit in the pla irq0 interrupt service routine to clear an edge triggered pla irq0 interrupt. 16 irq1clri a 1 must be written to this bit in the external irq1 interrupt service routine to clear an edge triggered irq1 interrupt. 15 to 14 reserved these bits are reserved and should not be written to. 13 irq0clri a 1 must be written to this bit in the external irq0 interrupt service routine to clear an edge triggered irq0 interrupt. 12 to 0 reserved these bits are reserved and should not be written to. timers the aduc7023 has three general-purpose timer/counters: timer0, timer1, and timer2 or watchdog timer. these three timers in their normal mode of operation can be either free-running or periodic. in free-running mode, the counter decreases from the maximum value until zero scale and starts again at the minimum value. (it also increases from the minimum value until full scale and starts again at the maximum value.) in periodic mode, the counter decrements/increments from the value in the load register (txld mmr) until zero/full scale and starts again at the value stored in the load register. the timer interval is calculated as follows: ( ) clocksource prescaler txd interval = 08675-036 the value of a counter can be read at any time by accessing its value register (txval). when a timer is being clocked from a clock other than core clock, an incorrect value may be read (due to asynchronous clock system). in this configuration, txval should always be read twice. if the two readings are different, it should be read a third time to get the correct value. timers are started by writing in the control register of the corresponding timer (txcon). in normal mode, an irq is generated each time the value of the counter reaches zero when counting down. it is also generated each time the counter value reaches full scale when counting up. an irq can be cleared by writing any value to clear the register of that particular timer (txclri). when using an asynchronous clock-to-clock timer, the interrupt in the timer block can take more time to clear than the time it takes for the code in the interrupt routine to execute. ensure that the interrupt signal is cleared before leaving the interrupt service routine. this can be done by checking the irqsta mmr. timer0 (rtos timer) timer0 is a general-purpose, 16-bit timer (count-down) with a programmable prescaler (see figure 42 ). the prescaler source is the core clock frequency (hclk) and can be scaled by factors of 1, 16, or 256. timer0 can be used to start adc conversions as shown in the block diagram in figure 42 . 16-bit load 32.768khz oscillator uclk hclk prescaler /1, 16, or 256 16-bit down counter timer0 irq timer0 value adc conversion figure 42. timer0 block diagram the timer0 interface consists of four mmrs: t0ld, t0val, t0con, and t0clri. t0ld register name: t0ld address: 0xffff0300 default value: 0x0000 access: read/write t0ld is a 16-bit load register. t0val register name: t0val address: 0xffff0304 default value: 0xffff access: read t0val is a 16-bit read-only register representing the current state of the counter.
aduc7023 rev. b | page 83 of 96 t0con register name: t0con address: 0xffff0308 default value: 0x0000 access: r/w t0con is the configuration mmr described in table 100 . table 100. t0con mmr bit descriptions bit value description 15 to 8 reserved. 7 timer0 enable bit. this bit is set by the user to enable timer0. this bit is cleared by the user to disable timer0 by default. 6 timer0 mode. this bit is set by the user to operate in periodic mode. this bit is cleared by the user to operate in free-running mode. default mode. 5 to 4 clock select bits. 00 hclk. 01 uclk. 10 internal 32768 hz oscillator. 11 reserved. 3 to 2 00 source clock/1. default value. 01 source clock/16. 10 source clock/256. 11 undefined. equivalent to 00. 1 to 0 reserved. t0clri register name: t0clri address: 0xffff030c default value: 0xxx access: write t0clri is an 8-bit register. writing any value to this register clears the interrupt. timer1 (general-purpose timer) timer1 is a general-purpose, 32-bit timer (count down or count up) with a programmable prescaler. the source can be the 32 khz external crystal, the undivided system, the core clock, or p1.1 (maximum frequency 44 mhz). this source can be scaled by a factor of 1, 16, 256, or 32,768. the counter can be formatted as a standard 32-bit value or as hours, minutes, seconds, hundredths. timer1 has a capture register (t1cap) that can be triggered by a selected irq source initial assertion. this feature can be used to determine the assertion of an event more accurately than the precision allowed by the rtos timer when the irq is serviced. timer1 can be used to start adc conversions as shown in the block diagram in figure 43 . 08675-037 32khz oscillator hclk uclk p1.1 irq[19:0] prescaler /1, 16, 256, or 32,768 32-bit up/down counter 32-bit load timer1 value capture timer1 irq adc conversion figure 43. timer1 block diagram the timer1 interface consists of five mmrs: t1ld, t1val, t1con, t1clri, and t1cap. t1ld register name: t1ld address: 0xffff0320 default value: 0x00000000 access: read/write t1ld is a 32-bit load register. t1val register name: t1val address: 0xffff0324 default value: 0xffffffff access: read t1val is a 32-bit read-only register that represents the current state of the counter. t1con register name: t1con address: 0xffff0328 default value: 0x00000000 access: read/write t1con is the configuration mmr described in table 101 .
aduc7023 rev. b | page 84 of 96 table 101. t1con mmr bit descriptions bit value description 31 to 18 reserved. 17 event select bit. this bit is set by the user to enable time capture of an event. this bit is cleared by the user to disable time capture of an event. 16 to 12 event select range, 0 to 31. these events are as described in table 87 . all events are offset by two, that is, event 2 in table 87 becomes event 0 for the purposes of timer1. 11 to 9 clock select. 000 core clock (hclk). 001 internal 32.768 khz crystal 010 uclk 011 p1.1 raising edge triggered. 8 count up. this bit is set by the user for timer1 to count up. this bit is cleared by the user for timer1 to count down by default. 7 timer1 enable bit. this bit is set by the user to enable timer1. this bit is cleared by the user to disable timer1 by default. 6 timer1 mode. this bit is set by the user to operate in periodic mode. this bit is cleared by the user to operate in free-running mode. default mode. 5 to 4 format. 00 binary. 01 reserved. 10 hours, minutes, seconds, hundredths (23 hours to 0 hour). 11 hours, minutes, seconds, hundredths (255 hours to 0 hour). 3 to 0 prescale. 0000 source clock/1. 0100 source clock/16. 1000 source clock/256. 1111 source clock/32,768. t1clri register name t1clri address 0xffff032c default value 0xxx access write t1clri is an -bit register writing any value to this register clears the timer1 interrupt t1cap register name t1cap address 0xffff0330 default value 0x00000000 access read t1cap is a 32-bit register it holds the value contained in t1val when a particular event occurrs this event must be selected in t1con timer2 (watchdog time) timer2 has two modes of operation normal mode and watchdog mode the watchdog timer is used to recover from an illegal software state when enabled, it requires periodic servicing to prevent it from forcing a processor reset normal mode timer2 in normal mode is identical to timer0, except for the clock source and the count-up functionality. the clock source is 32 khz from the pll and can be scaled by a factor of 1, 16, or 256 (see figure 44 ). 08675-038 32.768khz prescaler 1, 4, 16, or 256 16-bit up/down counter 16-bit load timer2 value timer2 irq watchdog reset figure 44. timer2 block diagram watch do g mo d e watchdog mode is entered by setting bit 5 in the t2con mmr. timer2 decreases from the value present in the t2ld register until 0. t2ld is used as the timeout. the maximum timeout can be 512 sec using the prescaler/256, and full-scale in t2ld. timer3 is clocked by the internal 32 khz crystal when operating in the watchdog mode. to enter watchdog mode successfully, bit 5 in the t2con mmr must be set after writing to the t2ld mmr. if the timer reaches 0, a reset or an interrupt occurs, depending on bit 1 in the t2con register. to avoid reset or interrupt, any value must be written to t2clri before the expiration period. this reloads the counter with t2ld and begins a new timeout period. when watchdog mode is entered, t2ld and t2con are write- protected. these two registers cannot be modified until a reset clears the watchdog enable bit, which causes timer2 to exit watchdog mode. the timer2 interface consists of four mmrs: t2ld, t2val, t2con, and t2clri.
aduc7023 rev. b | page 85 of 96 t2ld register name: t2ld address: 0xffff0360 default value: 0x0000 access: read/write t2ld is a 16-bit register load register. t2val register name: t2val address: 0xffff0364 default value: 0xffff access: read t2val is a 16-bit read-only register that represents the current state of the counter. t2con register name: t2con address: 0xffff0368 default value: 0x0000 access: read/write t2con is the configuration mmr described in table 102 . table 102. t2con mmr bit descriptions bit value description 15 to 9 reserved. 8 count up. this bit is set by the user for timer2 to count up. this bit is cleared by the user for timer2 to count down by default. 7 timer2 enable bit. this bit is set by the user to enable timer2. this bit is cleared by user to disable timer2 by default. bit value description 6 timer2 mode. this bit is set by user to operate in periodic mode. this bit is cleared by the user to operate in free-running mode. default mode. 5 watchdog mode enable bit. this bit is set by the user to enable watchdog mode. this bit is cleared by the user to disable watchdog mode by default. 4 secure clear bit. this bit is set by the user to use the secure clear option. this bit is cleared by the user to disable the secure clear option by default. 3 to 2 prescale. 00 source clock/1 by default. 01 source clock/16. 10 source clock/256. 11 undefined. equivalent to 00. 1 watchdog irq option bit. this bit is set by the user to produce an irq instead of a reset when the watchdog reaches 0. this bit is cleared by the user to disable the irq option. 0 reserved. t2clri register name: t2clri address: 0xffff036c default value: 0xxx access: write t2clri is an 8-bit register. writing any value to this register on successive occassions clears the timer2 interrupt in normal mode or resets a new timeout period in watchdog mode . the user must perform successive writes to this register to ensure resetting the timeout period.
aduc7023 rev. b | page 86 of 96 secure clear bit (watchdog mode only) the secure clear bit is provided for a higher level of protection. when set, a specific sequential value must be written to t2c lri to avoid a watchdog reset. the value is a sequence generated by the 8-bit linear feedback shift register (lfsr) polynomial = x8 + x6 + x5 + x + 1 shown in figure 45 . 08675-039 clock qd 4 qd 5 qd 3 qd 7 qd 6 qd 2 qd 1 qd 0 figure 45. 8-bit lfsr the initial value or seed is written to t2clri before entering watchdog mode. after entering watchdog mode, a write to t2clri m ust match this expected value. if it matches, the lfsr is advanced to the next state when the counter reload happens. if it fails t o match the expected state, a reset is immediately generated, even if the count has not yet expired. th e value 0x00 should not be used as an initial seed due to the properties of the polynomial. the value 0x00 is always guarante ed to force an immediate reset. the value of the lfsr cannot be read; it must be tracked/generated in software. an example of a sequence follows: 1. enter initial seed, 0xaa, in t2clri before starting timer2 in watchdog mode. 2. enter 0xaa in t2clri; timer2 is reloaded. 3. enter 0x37 in t2clri; timer2 is reloaded. 4. enter 0x6e in t2clri; timer2 is reloaded. 5. enter 0x66. 0xdc was expected; the watchdog resets the chip.
aduc7023 rev. b | page 87 of 96 hardware design considerations power supplies the aduc7023 operational power supply voltage range is 2.7 v to 3.6 v. separate analog and digital power supply pins (av dd and iov dd , respectively) allow av dd to be kept relatively free of noisy digital signals often present on the system iov dd line. in this mode, the part can also operate with split supplies, that is, it can use different voltage levels for each supply. for example, the system can be designed to operate with an iov dd voltage level of 3.3 v while the av dd level can be at 3 v, or vice versa. a typical split supply configuration is shown in figure 46 . 08675-041 aduc7023 iov dd av dd gnd ref agnd iognd 0.1f 0.1f 0.1f 10f 10f digital supply analog supply figure 46. external dual supply connections as an alternative to providing two separate power supplies, the user can reduce noise on av dd by placing a small series resistor and/or ferrite bead between av dd and iov dd , and then decoupling av dd separately to ground. an example of this configuration is shown in figure 47 . with this configuration, other analog circuitry (such as op amps, voltage refere nce, and others) can be powered from the av dd supply line as well. 08675-054 aduc7023 iov dd av dd gnd ref agnd refgnd iognd 0.1f 0.1f 0.1f 1.6v 10f 0.1f digital supply bead 10f figure 47. external single supply connections in both figure 46 and figure 47 , a large value (10 f) reservoir capacitor sits on iov dd , and a separate 10 f capacitor sits on av dd . in addition, local small-value (0.1 f) capacitors are located at each av dd and iov dd pin of the chip. as per standard design practice, include all of these capacitors and ensure the smaller capacitors are close to each av dd pin with trace lengths as short as possible. connect the ground terminal of each of these capacitors directly to the underlying ground plane. finally, the analog and digital ground pins on the aduc7023 must be referenced to the same system ground reference point at all times. iov dd supply sensitivity the iov dd supply is sensitive to high frequency noise because it is the supply source for the internal oscillator and pll circuits. when the internal pll loses lock, the clock source is removed by a gating circuit from the cpu, and the arm7tdmi core stops executing code until the pll regains lock. this feature is to ensure that no flash interface timings or arm7tdmi timings are violated. typically, frequency noise greater than 50 khz and 50 mv p-p on top of the supply causes the core to stop working. if decoupling values recommended in the power supplies section do not sufficiently dampen all noise soures below 50 mv on iov dd , a filter such as the one shown in figure 48 is recommended. 0 8675-042 aduc7023 iov dd iognd 0.1f 0.1f 10f 1h digital supply figure 48. recommended iov dd supply filter linear voltage regulator each aduc7023 requires a single 3.3 v supply, but the core logic requires a 2.6 v supply. an on-chip linear regulator generates the 2.6 v from iov dd for the core logic. the lv dd pin is the 2.6 v supply for the core logic. an external compensation capacitor of 0.47 f must be connected between lv dd and dgnd (as close as possible to these pins) to act as a tank of charge, as shown in figure 49 . 08675-043 aduc7023 lv dd dgnd 0.47f figure 49. voltage regulator connections the lv dd pin should not be used for any other chip. it is also recommended to use excellent power supply decoupling on iov dd to help improve line regulation performance of the on-chip voltage regulator.
aduc7023 rev. b | page 88 of 96 grounding and board layout recommendations as with all high resolution data converters, special attention must be paid to grounding and pc board layout of the aduc7023-based designs to achieve optimum performance from the adcs and dacs. although the parts have separate pins for analog and digital ground (agnd and dgnd), the user must not tie these to two separate ground planes unless the two ground planes are connected very close to the part. this is illustrated in the simplified example shown in figure 50 a. in systems where digital and analog ground planes are connected together somewhere else (at the system power supply, for example), the planes cannot be reconnected near the part because a ground loop would result. in these cases, tie all the aduc7023 agnd and dgnd pins to the analog ground plane, as illustrated in figure 50 b. in systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board so that digital return currents do not flow near analog circuitry (and vice versa). the aduc7023 can then be placed between the digital and analog sections, as illustrated in figure 50 c. 08675-044 a. place analog components here place digital components here agnd dgnd b. place analog components here place digital components here agnd dgnd c. place analog components here place digital components here dgnd figure 50. system grounding schemes in all of these scenarios, and in more complicated real-life applications, users should pay particular attention to the flow of current from the supplies and back to ground. make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. for example, do not power components on the analog side (as seen in figure 50 b) with iov dd because that would force return currents from iov dd to flow through agnd. avoid digital currents flowing under analog circuitry, which can occur if a noisy digital chip is placed on the left half of the board (shown in figure 50 c). if possible, avoid large discontinuities in the ground plane(s) such as those formed by a long trace on the same layer, because they force return signals to travel a longer path. in addition, make all connections to the ground plane directly, with little or no trace separating the pin from its via to ground. when connecting fast logic signals (rise/fall time < 5 ns) to any of the aduc7023 digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the input pins of the part. a value of 100 or 200 is usually sufficient enough to prevent high speed signals from coupling capacitively into the part and affecting the accuracy of adc conversions. clock oscillator the clock source for the aduc7023 can be generated by the internal pll or by an external clock input. to use the internal pll, connect a 32.768 khz parallel resonant crystal between xclki and xclko, and connect a capacitor from each pin to ground, as shown in figure 51 . the crystal allows the pll to lock correctly to give a frequency of 41.78 mhz. if no external crystal is present, the internal oscillator is used to give a typical frequency of 41.78 mhz 3%. 08675-045 aduc7023 to internal pll 12pf xclki 32.768khz 12pf xclko figure 51. external parallel resonant crystal connections to use an external source clock input instead of the pll (see figure 52 ), bit 1 and bit 0 of pllcon must be modified. the external clock uses p1.1 and xclk. 08675-046 aduc7023 to frequency divider xclko xclki xclk external clock source figure 52. connecting an external clock source using an external clock source, the aduc7023 specified operational clock speed range is 50 khz to 44 mhz 1%, which ensures correct operation of the analog peripherals and flash/ee.
aduc7023 rev. b | page 89 of 96 08675-047 io v dd 3.3 v 2.6v 2.40v typ 2.40v typ 64ms typ lv dd por rst 0.12ms typ power-on reset operation an internal power-on reset (por) is implemented on the aduc7023. for lv dd below 2.40 v typical, the internal por holds the part in reset. as lv dd rises above 2.40 v, an internal timer times out for typically 64 ms before the part is released from reset. the user must ensure that the power supply iov dd has reached a stable 2.7 v minimum level by this time. likewise, on power-down, the internal por holds the part in reset until lv dd has dropped below 2.40 v. figure 53 illustrates the operation of the internal por in detail. figure 53. internal power-on reset operation
aduc7023 rev. b | page 90 of 96 typical system configuration a typical aduc7023 configuration is shown in figure 54 . it summarizes some of the hardware considerations. the bottom of the lfcsp package has an exposed pad that needs to be soldered to a metal plate on the board for mechanical reasons. the metal plate of t he board can be connected to ground. 0 8 6 7 5 - 0 5 5 av dd aduc7023 p0.5 / sda0 / plai[ 1 ] / com p out xclki xclko rtck tms p0.0 / n trst/ adc busy /plai[8]/bm p0.1/plai[9]/tdo p0.2/plao[8]/tdi p0.3/plao[9]/tck p1.2/adc4/irq2/plai[3]/eclk p1.3/adc5/irq3/plai[4] v ref adc0 adc1 adc2/cmp0 adc3/cmp1 agnd p0.6/miso/scl1/plai[2] p0.7/miso/sda1/plao[0] p1 .0 / spiclk/ pwm 0 / pla o[ 1 ] p1 .1 / ss/ irq1 / pwm 1 / plao[ 2 ] / t1 dgnd iov dd lv dd rst gnd ref dac0 dac1 dac2 dac3 p0.4/ irq0/ scl0/ plai[0]/ conv pull-ups for i 2 c pins figure 54. typical system configuration
aduc7023 rev. b | page 91 of 96 development tools pc-based tools four types of development systems are available for the aduc7023 family. the aduc7023 quickstart plus is intended for new users who want to have a comprehensive hardware development environment. these systems consist of the following pc-based (windows? compatible) hardware and software development tools. hardware the hardware sytsem uses the aduc7023 evaluation board, aserial port programming cable, and a rdi-compliant jtag emulator (included in the aduc7023 quickstart plus only). software the software system has an integrated development environment, incorporating an assembler, compiler, and nonintrusive jtag-based debugger. the software sytem uses a serial downloader software and example code. miscellaneous the miscellaneous systems use cd-rom documentation. in-circuit i 2 c downloader an i 2 c-based serial downloader is available at www.analog.com . this software requires an usb-to-i 2 c adaptor board available from analog devices. the part number for this usb-to-i 2 c adapter is usb-i2c/lin-conv-z.
aduc7023 rev. b | page 92 of 96 outline dimensions 111808-a 0.50 bsc bottom view top view pin 1 indicator exposed pad p i n 1 i n d i c a t o r seating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.23 0.18 6.10 6.00 sq 5.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 0.25 min 4.45 4.30 sq 4.25 compliant to jedec standards mo-220-wjjd. 40 1 11 20 21 30 31 10 figure 55. 40-lead frame chip scale package [lfcsp_wq] 6 mm x 6 mm body, very thin quad (cp-40-10) dimensions shown in millimeters compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bottom view top view pin 1 indi c ator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r 3.65 3.50 sq 3.45 s eating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min figure 56. 32-lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very thin quad (cp-32-11) dimensions shown in millimeters
aduc7023 rev. b | page 93 of 96 ordering guide model 1 adc channels dac channels flash/ ram gpio downloader temperature range package description package option ordering quantity ADUC7023BCP6Z62I 12 4 62 kb/8 kb 20 i 2 c ?40c to +125c 40-lead lfcsp_wq cp-40-10 490 ADUC7023BCP6Z62Irl 12 4 62 kb/8 kb 20 i 2 c ?40c to +125c 40-lead lfcsp_wq cp-40-10 2,500 ADUC7023BCP6Z62Ir7 12 4 62 kb/8 kb 20 i 2 c ?40c to +125c 32-lead lfcsp_wq cp-32-10 750 aduc7023bcpz62i 12 4 62 kb/8 kb 12 i 2 c ?40c to +125c 32-lead lfcsp_wq cp-32-11 490 aduc7023bcpz62i-rl 8 4 62 kb/8 kb 12 i 2 c ?40c to +125c 32-lead lfcsp_wq cp-32-11 5,000 aduc7023bcpz62i-r7 8 4 62 kb/8 kb 12 i 2 c ?40c to +125c 32-lead lfcsp_wq cp-32-11 1,500 eval-aduc7023qspz aduc7023 quickstart plus development system using 32-pin aduc7023 eval-aduc7023qspz1 aduc7023 quickstart plus development system using 40-pin aduc7023 1 z = rohs compliant part.
aduc7023 rev. b | page 94 of 96 notes
aduc7023 rev. b | page 95 of 96 notes
aduc7023 rev. b | page 96 of 96 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08675-0-7/10(b)

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